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Verilog HDL实现的I2C Slave模拟
Verilog HDL实现的I2C Slave模拟-achieve the Verilog HDL simulation I2C Slave
- 2022-11-26 13:05:03下载
- 积分：1
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TLC1620
基于FPGA的Verilog语言实现的六十进制计数器(FPGA-based Verilog language implementation of six decimal counter)
- 2015-04-23 16:23:15下载
- 积分：1
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spi_test
说明： 基于fpga的spi通信测试 可与stm32进行spi通信测试(SPI communication test based on FPGA can test SPI communication with stm32)
- 2020-06-20 21:00:01下载
- 积分：1
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一个使用VHDL设计的具有强大功能的32位CPU，这个文件包含了在Altera公司的ep1c20 FPGA的位码文件和配置文件，可以直接下载使用！...
一个使用VHDL设计的具有强大功能的32位CPU，这个文件包含了在Altera公司的ep1c20 FPGA的位码文件和配置文件，可以直接下载使用！-A VHDL design with the use of powerful 32-bit CPU, this document contains Altera Corporation in the ep1c20 FPGA code and configuration files, you can direct download!
- 2022-09-14 09:40:03下载
- 积分：1
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Altera company s FPGA using VHDL to the development, use quartus2 9.0 software E...
使用altera公司的FPGA进行VHDL开发，使用quartus2 9.0 软件在EP1C3T144C8开发板上实现跑马灯输出。-Altera company s FPGA using VHDL to the development, use quartus2 9.0 software EP1C3T144C8 Development Board to achieve ticker output.
- 2022-02-02 20:51:33下载
- 积分：1
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mig_7series_v1_9
DDR3控制器源码，针对XilinxFPGA的DDR3控制器的源码，已经验证通过。(DDR3 Controller，complete DDR3 controll，have pass verificaion.)
- 2016-08-16 09:27:43下载
- 积分：1
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适用于FPGA初学者,一个流水灯的程序,用VERILOG语言写的.
适用于FPGA初学者,一个流水灯的程序,用VERILOG语言写的.-Applicable to FPGA beginners, a procedure for light water, using the Verilog language.
- 2022-04-09 16:22:19下载
- 积分：1
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pdf
说明： 一种基于FPGA的调频连续波方位向多通道
FMCW SAR的实时成像信号处理方法及FPGA，包
括：步骤一、计算重构矩阵；步骤二、重构方位向
多通道数据，包括：步骤2 .1、对各个通道的回波
数据沿方位向分别间隔补零，并进行方位向傅里
叶变换；步骤2 .2、将方位向傅里叶变换之后各个
通道方位向相同位置的点组合为一个向量并与
重构矩阵相乘，得到重构完成的方位向数据；(An azimuth multichannel FMCW based on FPGA
FMCW SAR real-time imaging signal processing method and FPGA, package
Including: Step 1: calculate the reconstruction matrix; step 2: reconstruct the orientation
Multichannel data, including: step 2.1, echo of each channel
The data is compensated with zero along the azimuth direction respectively, and the azimuth Fourier is carried out
Step 2.2, after the azimuth Fourier transform
The points of the same position in the channel azimuth are combined into a vector and are connected withThe reconstruction matrix is multiplied to get the reconstructed azimuth data
Step 2.3. Repeat step 2.3 for the data of different distance gates)
- 2020-02-07 19:47:41下载
- 积分：1
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shiyanc
说明： 希望对VHDL的学习大家有帮助，望大家指出错误，浮想交流！(We want to learn VHDL help, hope you point out an error, daydreams exchange!)
- 2011-04-14 09:10:28下载
- 积分：1
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This is is a bridge IP core to interface the Tensilica PIF bus protocol with the...
This is a bridge IP core to interface the Tensilica PIF bus protocol with the OpenCores WishBone. It currently supports single-cycle as well as burst transfer operations. The core has been tested in a master-PIF slave-WB configuration.-This is is a bridge IP core to interface the Tensilica PIF bus protocol with the OpenCores WishBone. It currently supports single-cycle as well as burst transfer operations. The core has been tested in a master-PIF slave-WB configuration.
- 2022-04-07 07:47:24下载
- 积分：1
