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RobustVerilog_free1.2_win
RobustVerilog生成verilog工具(RobustVerilog version)
- 2021-01-22 18:18:41下载
- 积分：1
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cnt60
六十进制计数器，VHDL编写的计数器，本科电子的可能有些实验可以用到(counter Possible experiments of undergraduate electronics can be used)
- 2021-04-07 11:59:01下载
- 积分：1
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source
ＦＰＧＡ与ＳＤＲＡＭ 的 ＶＨＤＬ 接口设计(ｔｈｅ interface of FPGA and SDRAM)
- 2012-03-28 22:17:19下载
- 积分：1
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主要是RS
主要是RS-232串行接口技术并且通过了串行收发器UART的开发实例演示了接口设计的基本步骤程序-Is RS-232 serial interface technology and, through a serial UART transceiver development of interface design examples demonstrate the basic steps of the procedure
- 2022-03-17 15:36:56下载
- 积分：1
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Verilog_135example
关于硬件描述语言Verilog的135个经典实例，从易到难，对Verilog的编程有很大的帮助。(About the Verilog hardware description language 135 classic example, from easy to difficult, for Verilog programming of great help.)
- 2013-06-17 10:29:43下载
- 积分：1
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3FP
一个三分频verilog模块，可以用来学习基本结构。(A three points frequency verilog module can be used to study the basic structure.)
- 2013-08-25 00:41:29下载
- 积分：1
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基于DE2开发板，视频图像显示设计源代码，代码调试成功
基于DE2开发板，视频图像显示设计源代码，代码调试成功-based DE2 development board ,it is vhdl resourse code
- 2022-03-15 06:09:25下载
- 积分：1
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DIGITAL-PID
Use verilog language design DIGITAL-PID source
- 2016-12-26 09:41:15下载
- 积分：1
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src
假设每个从设备中有可访问APB寄存器16个，位宽均为32比特，16个寄存器的访问地址计算方式为 基址 + 寄存器编号左移２位（byte 偏移）(Assuming that there are 16 accessible APB registers in each slave device, the bit width is 32 bits, and the access address of 16 registers is calculated by base address + register number left shift 2 bits (byte offset).)
- 2020-12-15 13:49:14下载
- 积分：1
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LCD_test
this a example for the LCD for altera FPGA cyclone ii EP2C8. implemented in verilog. tested using altera EP2C8 fpga
- 2013-07-25 14:43:43下载
- 积分：1
