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ml505_mig_design
Xilinx开发板ML505的DDRII示例程序，使用Verilog，调用MIG，编译环境ISE11.1(Xilinx ML505 development board of DDRII sample program, using Verilog, called MIG, build environment ISE11.1)
- 2010-05-13 02:39:04下载
- 积分：1
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FPGA-Design
自己搜集的一些FPGA指南教程，包括一些高工们的经验之谈、设计原则，目前正在学习，有一定帮助，分享给大家(Gather their own of some FPGA guide tutorial, including some senior engineers are the voice of experience, design principles, are learning to have some help, to share to everyone)
- 2012-11-06 10:58:54下载
- 积分：1
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mux8to1_with_if
this code to input 8 different data and make them out sequentialy
- 2015-02-19 10:54:20下载
- 积分：1
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alu
this file is vhdl code of alu
- 2016-05-29 16:35:58下载
- 积分：1
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track_version2
说明： fpga实现相关滤波算法中的CSK算法，采用仿真的方式验证结果
fpga是xilinx
仿真工具是vivado2018.2
语言是verilog(The CSK algorithm is implemented in FPGA, and the results are verified by simulation
FPGA is Xilinx
The simulation tool is vivado 2018.2
Language is Verilog)
- 2021-04-29 16:08:42下载
- 积分：1
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StandardSystemVerilog
这本书主要描述了如何使用system Verilog 建立测试平台和行为级模型(This book will describe how to use the system Verilog test bench and the establishment of behavioral models)
- 2010-05-12 10:35:54下载
- 积分：1
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prob1
UART program for fun(UART)
- 2009-11-18 10:26:04下载
- 积分：1
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include UART port of VERILOG source, the program tested in FPGA, as chip design,...
包含UART口的VERILOG源程序，该程序在FPGA上验证通过，可作为芯片设计，或FPGA设计的一个完整IP核，硬件设计的兄弟们可参考一下。-include UART port of VERILOG source, the program tested in FPGA, as chip design, or FPGA design of a complete IP cores, hardware design brothers can make reference.
- 2022-06-01 13:44:15下载
- 积分：1
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移位相加硬件乘法器,基于FPGA的VHDL语言编写的,含有全部文件
移位相加硬件乘法器,基于FPGA的VHDL语言编写的,含有全部文件-displacement add hardware multiplier, based on FPGA VHDL prepared, containing all the documents
- 2022-06-19 21:07:11下载
- 积分：1
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OFDM系统中的相位跟踪模块（Phase_Tracking）的FPGA实现
OFDM系统中的相位跟踪模块（Phase_Tracking）的FPGA实现-Phase_Tracking in OFDM sysytems
- 2022-10-06 04:25:03下载
- 积分：1
