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verilog 232串口收发程序 在开发板上测试成功过
verilog 232串口收发程序 在开发板上测试成功过-verilog 232 serial port transceiver program already had some success in the development of on-board test ^ ^
- 2022-02-11 11:33:57下载
- 积分：1
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VHDLaVerilogcomplie(20151022105744)
一个关于VERILOG与VHDL混合编程，混合验证的资料(A hybrid programming on VERILOG and VHDL, mixed verification data)
- 2015-12-14 17:19:26下载
- 积分：1
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XilinxISE9.2andChinpScopePro9.2Sn
Xilinx ISE 9.2 and ChinpScope Pro 9.2 Sn
- 2021-03-29 15:29:11下载
- 积分：1
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Xilinx-Timing
Xilinx FPGA 时序约束资料，原厂出品，经典不需要理由(Xilinx FPGA timing constraint information, original, classic no reason)
- 2013-05-17 09:31:26下载
- 积分：1
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使用VHDL实现三角函数的计算
为了便于计算结果在FPGA中后续的计算和ip核中的调用，本代码输入信号为普通浮点型数据，输出为32位表示的浮点型数据。
- 2022-07-21 05:59:31下载
- 积分：1
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Comparator for Quartus
Comparator for Quartus
- 2022-06-21 21:12:14下载
- 积分：1
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modulationshaped
基带数字信号通过成形滤波（选用升余弦滚降函数）然后进行载波调制(Base-band digital signal through the shaping filter (raised cosine roll-off optional function) and then proceed to carrier modulation)
- 2007-10-31 15:27:18下载
- 积分：1
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AT070TN83
at070tn83 800x480 tft lcd verilog 測試 quartus 文件 (800x480 tft lcd at070tn83 testing project file)
- 2020-12-07 15:39:21下载
- 积分：1
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6通道正弦波发生器，产生频率，相位，幅值都可调的正弦波形...
6通道正弦波发生器，产生频率，相位，幅值都可调的正弦波形-6-channel sine wave generator, resulting in frequency, phase, amplitude of the sinusoidal waveform are adjustable
- 2022-10-22 04:00:03下载
- 积分：1
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AD_FIFO
简单的Verilog程序，针对音频实验板的AD到DA调通试验，下载执行前请按照自己试验环境更改设置(Simple Verilog program for test the AD to DA loop of universal audio test platform.
Please configure it according to the test environment before download and implement the program to FPGA)
- 2013-01-26 00:47:37下载
- 积分：1
