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VHDL开发的计数器。源程序不复杂,应该都能看懂。最重要的注意:是时序问题
VHDL开发的计数器。源程序不复杂,应该都能看懂。最重要的注意:是时序问题-VHDL development of the counter. Source code is not complicated, should be able to understand. The most important Note : Timing is the issue
- 2022-05-14 00:07:18下载
- 积分:1
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PL_2FSK
基于VHDl的2FSK调制!用的是altera的quartus11软件(Based on VHDl the 2FSK modulation)
- 2012-12-13 17:20:54下载
- 积分:1
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descripe by the VHDL to drive the LCD cm12864,based on the FSM convertor,achieve...
cm12864液晶显示器的vhdl驱动代码,基于状态机的转换,实现显示功能。-descripe by the VHDL to drive the LCD cm12864,based on the FSM convertor,achieve the display function.
- 2022-12-01 22:05:03下载
- 积分:1
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110819_1
基于sopc的lcd时钟,开发工具为nios ii和quartus ii9.0(Based on sopc the lcd clock, development tools for the nios ii and quartus ii9.0)
- 2011-08-22 10:28:50下载
- 积分:1
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实用的程序代码,希望对大家有用,已经调试通过
实用的程序代码,希望对大家有用,已经调试通过-Practical program code, in the hope that useful to everybody, has debugging through
- 2022-09-21 12:35:03下载
- 积分:1
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ModelSim-gaojishiyong--Camp
FPGA开发仿真工具modelsim的高级进阶教程,包括如何写脚本文件和后台批处理文件(FPGA Development Advanced simulation tools modelsim tutorial, including how to write a script file and back-office batch file)
- 2012-05-09 23:52:21下载
- 积分:1
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jesd204_0_ex
说明: jesd204b接收部分程序和带仿真历程(Jesd204b receiving part program and simulation process)
- 2020-11-26 14:49:31下载
- 积分:1
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由VHDL 语言实现的D触发器利用的是QUARTUES环境已经得到验证
由VHDL 语言实现的D触发器利用的是QUARTUES环境已经得到验证-By the VHDL language using the D flip-flop is QUARTUES environment has been tested
- 2022-05-08 21:19:33下载
- 积分:1
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Chapter10
第十章的代码。
本书通过100多个模块实例,详细地讲解了Verilog HDL程序设计语言,全书共分13章,内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等,实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例模块相应的Testbench,所举实例具有很强的实用性和代表性,每个实例均给出了介绍、功能分析、程序代码和结果演示(Chapter X code. This book by more than 100 module instance, explain in detail the Verilog HDL programming language, the book is divided into 13 chapters, covering basic concepts VerilogHDL languages, modeling, synchronous design, asynchronous design, functional verification, etc. Examples include a variety of additions device/counters, multipliers/dividers, encoders/decoders, state machines, SPIMaster Controller, I2C Master controller, CAN ProtocolController, Memory modules, JPEG image compression module, encryption module, ATA controller, 8-bit RISC-CPU etc. and the various instances of the corresponding module Testbench, The examples are highly practical and representation, each instance of it all gives the introduction, functional analysis, program code and the results demonstrate)
- 2009-11-17 13:52:32下载
- 积分:1
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shift_regeister
用blockram实现移位寄存器,开发语言为verilog hdl(Shift register with blockram achieve the development language for the verilog hdl)
- 2020-08-13 22:18:29下载
- 积分:1