-
ise
xilinx的时序约束实验，通过阅读本文档，你可以用全局时序约束来轻松提高已有的项目的系统时钟频率，同时你还可以用映射后静态时序报告以及布局布线后静态时序报告来分析你的设计性能(Xilinx timing constraints of the experiment, by reading this document, you can use the overall timing constraints to easily enhance existing projects the system clock frequency, at the same time you can also use static timing report after mapping, as well as after placement and routing static timing analysis report to you design performance)
- 2007-09-20 14:30:52下载
- 积分：1
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MTKhardwaretraing
MTK平台硬件培训MTK平台硬件培训MTK平台 GSM双频手机接收信号
处理流程MTK平台 GSM双频手机接收信号
处理流程
(MTK platform hardware training platform hardware training MTK MTK GSM dual-band mobile phone platform to receive the signal processing)
- 2010-08-05 00:12:33下载
- 积分：1
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16QAM
QAM调制模块，可用于Quartus仿真与fpga硬件实现。(QAM Modulation Mode, can be used for Quartus simulation and FPGA.)
- 2013-12-27 10:01:48下载
- 积分：1
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2MW_wind_grid_inverter
针对兆瓦级风电并网逆变器主电路研制中存在的并联扩容、开关频率较低和LCL滤波器难以优化设计等问题，提出了采用交流侧串接电感再进行并联的均流方案，采用载波移相技术提高变流器的等效开关频率，提出了LCL滤波器的设计原则，并给出了上述设计的理论依据和实现方法。通过对2兆瓦风电变流器主电路的仿真验证了上述技术方案。(MW-class wind power for grid-inverter main circuit of the parallel development of existing capacity, a lower switching frequency and LCL filter design difficult to optimize the problem, a series inductor AC side in parallel are further flow program, the use of carrier phase-shifting technology to enhance the equivalent converter switching frequency, a LCL filter design principles, and gives the above-mentioned theoretical basis for the design and implementation. 2 MW of wind power converter main circuit simulation program to verify the above-mentioned technology.)
- 2009-04-28 09:16:38下载
- 积分：1
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rc-evga-indtube
evga-indtube.h - Keytable for evga_indtube Remote Controller.
- 2015-04-16 11:06:12下载
- 积分：1
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程序采用VHDL：频率合成DDS主要调用LPM，
程序用VHDL实现：
频率合成，DDS
主要调用LPM-procedures using VHDL : frequency synthesis, DDS major call LPM
- 2023-07-07 03:20:03下载
- 积分：1
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用verilog语言编写的步进电机加减速控制算法 Motion_control
用verilog语言编写的步进电机加减速控制算法，可选择梯形曲线或S型曲线算法(Verilog language stepper motor acceleration and deceleration control algorithm, you can choose the trapezoidal curve or S-curve algorithm)
- 2021-03-19 15:39:19下载
- 积分：1
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FIR低
fir低通滤波器 用于dspbuilder pll：25ns data 400khz sin 10.8khz-fir low-pass filter for dspbuilder pll: 25ns data 400khz sin 10.8khz
- 2023-05-01 00:45:03下载
- 积分：1
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Synopsys-RTLSystemC
synopsys的systemc和RTl书籍清晰电子版，专业权威的EDA公司的培训资料(synopsys of systemc and RTl clear electronic version of books, professional authority of the EDA company' s training materials)
- 2010-08-11 11:49:49下载
- 积分：1
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Applicable to FPGA
适用于FPGA的SOPC方面的元器件添加，如COMPNENT-Applicable to FPGA-SOPC area to add components, such as COMPNENT
- 2023-06-11 11:30:03下载
- 积分：1
