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altera 公司的15IP源码
亲自测试还不错 有DIV, CONTER
altera 公司的15IP源码
亲自测试还不错 有DIV, CONTER-ALTERA the 15IP source personally tests are also good DIV, CONTER
- 2022-03-13 02:56:46下载
- 积分：1
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tlc549
数字电压表的实现，VHDL语言实现，AD采用TLC549，通过学习，了解AD采集过程(The realization of digital voltage meter, VHDL language, AD using TLC549, by learning to understand the acquisition process AD)
- 2009-07-09 09:15:15下载
- 积分：1
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failed to translate
用于FPGA实现单总线测温电阻DS18b20时序。在xilinx spartan 3中试过。-failed to translate
- 2022-01-20 22:48:28下载
- 积分：1
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Add_sub_struc
8位加减器，八位减法器与加法器，用过一个控制端可以自由变换，采用移位加法方式，用途广泛，利用减法位补码加法的理论实现。(8 addition and subtraction, eight subtractor and adder, used a control terminal can freely change the using Shift addition, a wide range of uses, the use of subtraction complement addition theory to achieve.)
- 2012-05-14 20:36:26下载
- 积分：1
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zhaozhou_verilog
usb3.0 物理层仿真，verilog编程(Start the physical simulation)
- 2014-04-04 11:49:09下载
- 积分：1
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math_real
in this code very useful for designing real number concept
- 2013-11-19 19:54:40下载
- 积分：1
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CameraLink_Oserdes2_test
40M时钟输入经过iserdes倍频到960M(input 40M o clock and output 960M )
- 2014-02-25 14:06:38下载
- 积分：1
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laplace
说明： Laplace可以应用于图像的锐化，根据其原理，对于Laplace后的图像同样可以进行边缘检测。(Laplace can be applied to image sharpening. According to its principle, edge detection can also be performed for images after Laplace.)
- 2020-07-15 18:28:50下载
- 积分：1
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对于多个子分频的Verilog代码
verilog分频器代码
分为偶数倍分频和奇数倍分频两个verilog源文件 附带一个说明文档-divider verilog code for multiple sub-divided into even and odd frequency divider several times with a two verilog source files documentation
- 2022-10-15 03:40:06下载
- 积分：1
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这是我的VHDL格式的电子密码锁源程序，请站长审核啊
这是我的VHDL格式的电子密码锁源程序，请站长审核啊-This is my VHDL source code format of the electronic lock, please review ah owners
- 2022-04-12 03:07:56下载
- 积分：1
