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used in the preparation of Verilog FLEX10K achieve simple CPU
用verilog编写在FLEX10K上实现的简易CPU-used in the preparation of Verilog FLEX10K achieve simple CPU
- 2022-03-25 10:21:37下载
- 积分：1
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In the FPGA to achieve the sound card interface, flower, filter comparators, the...
在FPGA上实现声卡接口，电子琴，滤波比较器，最终实现语音通信
-In the FPGA to achieve the sound card interface, flower, filter comparators, the eventual realization of voice communications
- 2022-01-25 20:35:57下载
- 积分：1
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DA(AD768)
AD768产生锯齿波的源码，DA转化的最基本操作。(AD768 sawtooth source code, the basic operation of DA conversion.)
- 2014-03-19 09:39:54下载
- 积分：1
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USB接口控制器参考设计，xilinx提供的VHDL源代码
USB接口控制器参考设计，xilinx提供的VHDL源代码-USB interface controller reference design for Xilinx VHDL source code
- 2022-12-12 09:35:03下载
- 积分：1
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Applicable to FPGA
适用于FPGA的SOPC方面的元器件添加，如COMPNENT-Applicable to FPGA-SOPC area to add components, such as COMPNENT
- 2023-06-04 02:30:03下载
- 积分：1
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zobrazenie_16_bit_cisla_paralel
16 bit switch input view in hexa format on 7seg display
- 2013-08-16 00:50:49下载
- 积分：1
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FM_DemodNew
FM接收机 基于FPGA的调频收音机的设计
用VEIRLOG语言编程，利用QUARTUSii与MODELSIM联合仿真(FM receiver on FPGA FM receiver design
With VEIRLOG language program, use QUARTUSii and MODELSIM joint simulation)
- 2021-04-07 12:49:01下载
- 积分：1
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Block-cipher-lock
密码锁verilog源代码，包括四个七段数码管显示模块，设置密码以及输入密码校验模块(Password lock Verilog source code, including four of seven digital tube display module, set the password and password verification module)
- 2014-01-11 23:57:19下载
- 积分：1
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stopwatch-based-on-VHDL
基于VHDL的电子秒表的设计，使用VHDL语言描述一个秒表电路，利用QuantusII软件进行源程序设计，编译，仿真，最后形成下载文件下载至装有FPGA芯片的实验箱，进行硬件测试，要求实现秒表功能。(Design of electronic stopwatch based on VHDL)
- 2013-11-27 15:42:41下载
- 积分：1
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NRZ_2_Manchester_Moore
this example exchanges the NRZ code to the MANCHESTER code with moore output
- 2010-01-29 18:46:08下载
- 积分：1
