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design of 1-bit memory using cmos logic
&单元格
- 2022-02-04 02:43:34下载
- 积分:1
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edge_detect_p
用于检测信号上升沿,输出与时钟相关的正脉冲(Detect the rising edge of the signal)
- 2012-03-27 14:49:21下载
- 积分:1
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VHDL实现PI调节的算法。内部使用整数计算,避开了浮点数的运算。仿真结果正确...
VHDL实现PI调节的算法。内部使用整数计算,避开了浮点数的运算。仿真结果正确-VHDL realize PI regulator algorithm. Internal use integer calculations to avoid the floating point arithmetic. The simulation results correctly
- 2022-02-05 16:23:16下载
- 积分:1
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gtx_drp
高速串行设计FPGA-GTX IP设置生成drp模块,可动态配置速率2.4Gbps,1.2Gbps,0.6Gbps,自适应链接(High-speed serial design FPGA-GTX IP setting generation drp module, dynamically configurable rate 2.4Gbps, 1.2Gbps, 0.6Gbps, adaptive link)
- 2021-01-19 22:38:43下载
- 积分:1
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UML_2_Pour_les_bases_de_donnees
UML2 apprendre a modeliser a l aide de UML
- 2014-02-25 01:32:23下载
- 积分:1
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irda.tar
depends on irda transmitter recever
- 2009-11-20 00:31:48下载
- 积分:1
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8051core-Verilog
8051core-Verilog FPGA
- 2021-02-02 21:59:59下载
- 积分:1
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基于fpga和xinlinx ise的usb端口vhdl程序,希望对你有所帮助!
基于fpga和xinlinx ise的usb端口vhdl程序,希望对你有所帮助!-VHDL program for USB port based fpga and xinlinx ise, wish help for you!
- 2022-02-05 00:39:46下载
- 积分:1
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multiply_8_VHDL
由8 位加法器构成的以时序方式设计的8 位乘法器,采用逐项移位相加的方
法来实现相乘的VHDL程序代码。包含几个小模块和一个顶层设计文件,运行可用。(an 8 bit multiplier combined with 8 bit adder using a design by way of timing,and it use a way of Itemized shift to implement the multiply.It include some little module and a top level design document.)
- 2014-04-11 16:58:04下载
- 积分:1
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以上是VHDL硬件描述语言写的一个简单锝路流水灯程序,希望对刚接触VHDL的朋友有一定帮助...
以上是VHDL硬件描述语言写的一个简单锝路流水灯程序,希望对刚接触VHDL的朋友有一定帮助-These are the VHDL hardware description language written in a simple flow path lights technetium procedures,刚接触VHDL want to have some friends to help
- 2023-08-06 14:45:02下载
- 积分:1