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FPGA的DDS发生器

于 2022-06-16 发布 文件大小:1.53 MB
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代码说明:

以DE2为开发平台,采用Veriolg语言编程,实现了DDS信号输出,频率,步进,波形输出均可调,采用Modelsim以及FPGA内嵌逻辑分析仪验证设计的正确性,可以满足一定的工程需求。

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