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LMS算法FPGA仿真
自适应滤波器算法LMS ,的FPGA实现,采用VERILOG实现。(LMS, an adaptive filter algorithm, is implemented on FPGA and VERILOG.)
- 2020-06-24 01:00:02下载
- 积分:1
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mimaiic
基于AT89C51的密码锁(掉电可记忆密码)的程序(Based on AT89C51 lock (down to remembering passwords) program)
- 2013-06-06 11:38:13下载
- 积分:1
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a good use of the Verilog Programming cpu procedures, we must make good use of.
一个很好的利用verilog编程实现的cpu程序,一定要好好利用。-a good use of the Verilog Programming cpu procedures, we must make good use of.
- 2023-03-28 18:35:03下载
- 积分:1
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src
yuv444 与yuv422相互转换verilog语言(yuv444 to yuv422)
- 2021-01-20 14:38:41下载
- 积分:1
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ps2
PS2键盘硬件模块控制器,主要实现硬件PS2键盘的控制,适合初学verilog学者实验。(PS2 keyboard controller hardware module, the main hardware PS2 keyboard control, suitable for beginners verilog scholar experiments.)
- 2014-09-16 19:06:23下载
- 积分:1
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medianfilter
图像滤波中的中值滤波,有效滤除椒盐噪声,使用verilog语言编写(Image filtering in the median filter, effectively filter out salt and pepper noise, using verilog language)
- 2011-10-13 17:08:48下载
- 积分:1
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PWM
通过一个计数器来实现输出信号的占空比要求,可以将duty_cycle分配到拨码开关上,LED分配到发光二极管上,然后调节拨码开关,即可看到LED的亮度发生变化.(The duty cycle of the output signal can be assigned to the dial switch by a counter, and the LED can be assigned to the light emitting diode. Then the brightness of the LED can be seen by adjusting the dial switch.)
- 2020-06-16 13:20:02下载
- 积分:1
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上海大学 Verilog PPT 适合初学者看 推荐
上海大学 Verilog PPT 适合初学者看 推荐 -Shanghai University Verilog PPT look recommended for beginners
- 2022-04-19 13:38:15下载
- 积分:1
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fifo16_16
异步的fifo,写时钟和读时钟相互独立,能够对数据进行缓存处理。希望对大家有用(Asynchronous fifo, write clock and the read clock independent of each other, capable of processing the data cache. I hope useful)
- 2020-10-26 10:49:59下载
- 积分:1
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traffic 2
说明: 实现主干道交通灯显示,以状态机程序实现,并用数码管进行红绿灯倒计时的显示,内置计数模块,交通灯控制模块,数码管显示模块,并对各模块用电路图的方式进行连接。对于学习VHDL语言有所帮助。(The main road traffic light display is realized by the state machine program, and the digital tube is used to display the traffic light countdown. The counting module, the traffic light control module and the digital tube display module are built in, and each module is connected by the circuit diagram. It is helpful for learning VHDL.)
- 2020-06-25 19:55:12下载
- 积分:1