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VHDL_Led control single light from right to left( điều khiển led sáng dồn từ phải sang trái)
- 2023-08-04 23:15:03下载
- 积分：1
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GBT-15946-2008GPIB
GBT 15946-2008 GPIB可编程仪器标准数字接口的高性能协议 概述 (GBT 15946-2008 GPIB Programmable Instruments standard digital interface for high-performance protocol Overview)
- 2012-08-30 11:49:29下载
- 积分：1
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10_ImageEdge
基于System Generator的图像处理工程,多媒体处理FPGA实现的源码,图像边缘提取(System Generator based image processing engineering, multimedia processing FPGA implementation source code, image edge extraction)
- 2020-10-23 20:27:22下载
- 积分：1
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5-15
用verilog语言实现基于DDS技术的余弦信号发生器，其输出位宽为16比特(Verilog language cosine signal generator based on DDS technology, the output bit width is 16 bits)
- 2013-04-18 22:58:05下载
- 积分：1
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以前学习VHDL语言时做的一个电子闹钟程序，可以实现时，分，秒的计时以及定时，校时，闹钟，整点报时的功能。...
以前学习VHDL语言时做的一个电子闹钟程序，可以实现时，分，秒的计时以及定时，校时，闹钟，整点报时的功能。-VHDL language before learning to do procedures in an electronic alarm clock, you can realize hours, minutes and seconds of time and from time to time, school time, alarm clock, the whole point timekeeping function.
- 2022-05-06 21:47:35下载
- 积分：1
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f500
verilog coding for butterworth filter with cut off
frequency with 500hz
- 2014-02-19 15:37:09下载
- 积分：1
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ArhivaAdrian
Anticipated Adder for Xilinx
- 2011-11-15 06:57:02下载
- 积分：1
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ISP的IP核，下载即可用，解压到指定目录下就可以了，参照里面的read me....
ISP的IP核，下载即可用，解压到指定目录下就可以了，参照里面的read me.-ISP of the IP core, can be used to download, unzip to the specified directory can be a light inside the read me.
- 2022-02-02 17:09:38下载
- 积分：1
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基于ＦＰＧＡ，实现了移位除法的功能，程序接口简单，十分好用，已经验证。...
基于ＦＰＧＡ，实现了移位除法的功能，程序接口简单，十分好用，已经验证。-Based on the FPGA, to achieve the division of functional shift, the program interface is simple, very easy to use, has already been verified.
- 2022-10-14 07:10:02下载
- 积分：1
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Modulator70
个人参与的某国家工程并行排序MATLAB程序，用于FPGA的RTLAB仿真，使用Simulink工具生成HDL代码。测试可用。(Individuals involved in sort of a national engineering parallel MATLAB programs for the FPGA RTLAB simulation, using the Simulink tool to generate HDL code. Test available.)
- 2011-07-29 15:16:30下载
- 积分：1
