-
Verilog written procedures for counting frequency meter module,
verilog写的频率计程序的计数模块,-Verilog written procedures for counting frequency meter module,
- 2022-03-20 18:03:19下载
- 积分：1
-
realization of the project document ARM system CPLD logic, external resources ha...
该工程文件实现ARM系统中CPLD的逻辑工作，起到外围资源的逻辑地址译码功能-realization of the project document ARM system CPLD logic, external resources have address decoding logic function
- 2022-02-05 23:05:52下载
- 积分：1
-
dvb_s2_ldpc_decoder_latest.tar
LDPC COded OFDM System
- 2013-02-09 21:41:33下载
- 积分：1
-
4：2优先编码器的VHDL代码
4：2优先编码设计中的VHDL来为每个输入分配优先级。在CMOS布局1复用器：还设计了4个
- 2022-02-11 13:12:33下载
- 积分：1
-
It is a fir to implement in a FPGA. It s not desenvolved for me it is a good wor...
It is a fir to implement in a FPGA. It s not desenvolved for me it is a good work of another person
- 2022-03-29 20:48:40下载
- 积分：1
-
3P3_wimdow
图像插值算法，窗口为3*3,用于图像的除去死点，以及提高清晰度或者使图像柔和(3*3 window)
- 2012-02-28 15:36:02下载
- 积分：1
-
ISPPCBforFPGA
Xilinx,Altera,ARM,AVR,S52,Lattice等系列FPGA的下载线电路图和PCB(Xilinx, Altera, ARM, AVR, S52, Lattice series FPGA download cable circuit diagram and PCB)
- 2009-12-14 16:55:35下载
- 积分：1
-
vhdl_lms
vhdl 语言实现的lms算法的自适应滤波器 两种实现方式 包括改进(VHDL language lms algorithm adaptive filter implemented in two ways including improved)
- 2012-04-26 18:15:02下载
- 积分：1
-
simpleCpu
relative cpu design implementation
- 2013-08-14 21:22:39下载
- 积分：1
-
vhdl编写的硬件乘法器
vhdl编写的硬件乘法器-prepared by the VHDL hardware multiplier
- 2022-01-26 07:31:00下载
- 积分：1
|
联系客服（QQ：3324461878）
