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实现控制8x8点阵动态显示字母的程序
基于CPLD的实现控制8x8点阵动态显示字母的程序，使用VHDL语言，通过调节分频系数可以实现点阵的变换速度，通过改变不同的状态可以让点阵显示不同的图案。
- 2022-03-19 00:46:52下载
- 积分：1
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Nios_II_uCOS
本源码为Nios II的开发示例,主要演示基于Nios II的uCOS的移植。开发环境QuartusII。
本示例十分经典，对基于SOPC开发的FPGA初学者有很大帮助。(The source code for the Nios II development of examples, mainly based on the Nios II shows the uCOS transplant. Development environment QuartusII. This example is very classic, FPGA-based SOPC development of great help for beginners.)
- 2009-12-18 14:08:40下载
- 积分：1
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LCD_1602
说明： 以ISE为开发环境，Verilog语言编写程序。功能：FPGA控制 LCD_1602动态显示秒表(In the development environment of ISE, Verilog language is used to write programs. Function: LCD_1602 dynamic display stopwatch controlled by FPGA)
- 2020-06-20 00:00:02下载
- 积分：1
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uart
一个实用的uart协议模块，使用verilog 实现(A practical uart protocol modules, use verilog to achieve)
- 2013-07-25 11:43:34下载
- 积分：1
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Automatic-washing-machine-controller
全自动洗衣机的控制器。
1.洗衣机的工作步骤为洗衣、漂洗和脱水三个过程，工作时间分别为：洗涤10秒，漂洗5秒，脱水5秒；
2.用一个按键实现洗衣程序的手动选择：A、单洗涤；B、单漂洗；C、单脱水；D、漂洗和脱水；E、洗涤、漂洗和脱水全过程；
3.用显示器件显示洗衣机的工作状态（洗衣、漂洗和脱水），并倒计时显示每个状态的工作时间，全部过程结束后，应提示使用者；
4.用一个按键实现暂停洗衣和继续洗衣的控制，暂停后继续洗衣应回到暂停之前保留的状态；
(Automatic washing machine controller. 1 washing machine work steps for the laundry, rinsing and dehydration three processes, working hours are as follows: washed for 10 seconds, rinse for 5 seconds, dehydrated five seconds 2 with a button to manually select the program to achieve laundry: A, single-washing B, single rinse C, a single dehydration D, rinsing and dehydration E, washing, rinsing and dehydration the whole process 3 with a display device display the working status of washing machine (laundry, rinsing and dehydration), and each state countdown show working hours, after the whole process should prompt the user 4 laundry with a button to pause and continue control of laundry, laundry should be back after a pause pause before continuing to retain the state )
- 2020-11-11 16:29:44下载
- 积分：1
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DVI_LED
基于DVI协议动态全彩LED大屏幕发送卡设计与实现,成本比较低,效果很好,可以实现高清视频(Dynamic full-color LED large screen based on the DVI protocol send a card design and relatively low cost, good effect, and can achieve high-definition video)
- 2012-08-03 13:08:44下载
- 积分：1
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"Verilog HDL Design Guide" 8
《Verilog HDL 程序设计教程》8-"Verilog HDL Design Guide" 8
- 2022-10-10 02:30:02下载
- 积分：1
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vga_demo2
VGA controller : Genarate a VGA signal from your inout information as color info of each pixel
- 2010-06-24 09:26:57下载
- 积分：1
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AMBA
AMBA总线规范，能对从事嵌入式的同行们有一些帮助，让大家更好的理解ARM 结构和AMBA 体系(AMBA Specification)
- 2012-12-06 20:35:22下载
- 积分：1
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DSP_INTERFACE
DSP与FPGA时序接口模块，已经经过测试，保证读写稳定(The Interface of DSP to FPGA)
- 2021-01-08 10:58:51下载
- 积分：1
