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[verilog]dcfifo_256x32
双时钟域FIFO(This is self-defined Dual-Clock FIFO, using logic lut resources.
Dual-Clock FIFO,
Depth: 256
Width: 32
USEDW: Y
FULLL:Y
EMPTY:Y)
- 2017-05-10 13:25:41下载
- 积分：1
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QuartusII brochure+ Chinese version of the manual is aimed at readers of Quartus...
QuartusII简介手册+中文版
本手册针对的读者是 Quartus II 软件的初学者，它概述了可编程逻辑设计中
Quartus II 软件的功能。 不过，本手册并不是 Quartus II 软件的详尽参考手
册。 相反，本手册只是一本指导书，它解释软件的功能以及显示这些功能如
何帮助您进行 FPGA 和 CPLD 设计。-QuartusII brochure+ Chinese version of the manual is aimed at readers of Quartus II software for beginners, it provides an overview of programmable logic design in Quartus II software. However, this manual is not the Quartus II software, a detailed reference manual. Instead, this manual is a guide book, which explained the functions of the software and show how these features help you to FPGA and CPLD design.
- 2022-07-12 19:32:51下载
- 积分：1
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fpga_sdram_inst
nios学习资料，fpga调用外部sdram实例，值得初学者下载。(nios learning materials, fpga call external sdram instance, it is worth beginners to download.)
- 2013-08-24 22:26:31下载
- 积分：1
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fpgaConfig_V1_2_SFLASH_20090507a
自己写的一个使用单片机配置FPGA的下位机C代码，使用一个C8051F330,外置SPI FLASH,通过串口可将程序写入FLASH,上电时自动加载到FPGA完成配置。(Wrote it myself, using a microcontroller to configure FPGA code for the next bit plane C, using a C8051F330, external SPI FLASH, the program is written through the serial port can be FLASH, power-on automatically loaded into the FPGA to complete the configuration.)
- 2021-02-16 07:29:47下载
- 积分：1
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four_interleaved
实现mimo-ofdm系统的交织功能，可供参考(Implement the mixed function of mimo- ofdm system, available for reference)
- 2013-03-30 09:22:40下载
- 积分：1
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this a fpga sparttan 3e based project in which
i have made a game based on vg...
this a fpga sparttan 3e based project in which
i have made a game based on vga interface .
this file is the main file included in the project.-this is a fpga sparttan 3e based project in which
i have made a game based on vga interface .
this file is the main file included in the project.
- 2023-09-06 13:30:04下载
- 积分：1
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基于ＦＰＧＡ平台，实现了直接数字频率合成。
基于ＦＰＧＡ平台，实现了直接数字频率合成。-FPGA-based platform, to achieve a direct digital frequency synthesis.
- 2022-03-01 23:16:21下载
- 积分：1
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ethernet_mac-master
说明： ethernet mac vhdl verilog basic
- 2019-03-30 15:47:25下载
- 积分：1
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DisplayPort Link training optimization
说明： 介绍了Displayport规格中lind training的背景研究，设计和实现。(As the requirement for bandwidth continues to increase in the video market, retaining
the signal integrity becomes increasingly more difficult. For many of todays
commonly used video interfaces, there are devices that can be used to assist in this
matter. However, the use of such a device is only partially documented in the DisplayPort
specification for the receiving image device, which means that the receiving
side of the video link is free to choose its own implementation. This report presents,
together with background research and design decisions, a suggestion for such an
implementation. This implementation would need to be compatible towards a wide
range of possible video Source devices and DisplayPort cables.)
- 2021-01-11 16:48:49下载
- 积分：1
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rtl
SPI verilog RTL code
- 2016-02-29 12:26:08下载
- 积分：1
