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Baseband_line_code
基于VHDL语言的基带线路码产生电路设计（毕业论文），内涵完整的源代码(Based on VHDL language baseband line code generation circuit design (Thesis), meaning the complete source code)
- 2010-07-03 22:38:09下载
- 积分：1
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Verilog Booth 型乘法器
此文件描述的 verilog booth 型乘法器的代码。源代码是模拟和验证效果会更好
- 2022-08-21 23:35:26下载
- 积分：1
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FPGA NIOS II W5500
Altera FPGA NIOS II 通过W5500芯片完成网络TCP/IP通讯。
- 2022-08-10 04:58:17下载
- 积分：1
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M_SSB_100
由乘法器组成 单边带信号产生的 仿真源代码 msm (Composed of single sideband signal by the multiplier generated simulation source code msm)
- 2007-07-25 14:59:29下载
- 积分：1
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自己写的Verilog实现状态机1101；用于Xilix的Basis2 开发板。
本实列自己写的状态机1101序列检测，已经在modesim上面测试通过，使用两个always块，一个写组合逻辑电路，一个为时序逻辑电路。需要的可以看看
- 2022-12-12 04:40:03下载
- 积分：1
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VHDL-Code-For-Full-Adder-By-Data-Flow-Modelling
VHDL Code For Full Adder By Data Flow Modelling
- 2013-11-08 00:39:04下载
- 积分：1
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DCM
fpga DCM使用教程 好几个文档 帮助您一次学会使用DCM(fpga the DCM using the tutorial a few documents to help you first learn to use the DCM)
- 2012-04-23 16:59:20下载
- 积分：1
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DW8051_ALL
包中包括,
DW8051完整的Verilog HDL代码
两本手册:
DesignWare Library DW8051 MacroCell, Datasheet
DesignWare DW8051 MacroCell Databook
三篇51论文:
基于IP 核的PSTN 短消息终端SoC 软硬件协同设计
Embedded TCP/ IP Chip Based on DW8051 Core
以8051为核的SOC中的万年历的设计 (DW8051 is designed by synopsys, and its instruction cycle is 4 clock, which lead to about 3 times faster than Intel 8051 with the same oscillator frequency. I writed ram, rom, some other perpherals such as DES, RNG, and its testbench, and it worked all right!)
- 2021-05-07 09:28:36下载
- 积分：1
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openmips
一个开源mips处理器verilog 源码(wishbone interface wishbone interface)
- 2020-08-16 15:48:32下载
- 积分：1
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hilbert_transformer.tar
hilbert 变换的vhdl源代码，来源于网上，本人也做过简单的8抽头的，但这个的算法还没搞懂，希望懂行的下载了研究一下，给个中文的简单的说明！(hilbert transform VHDL source code from the Internet, I have been a simple 8-tap, but even before they get to know this algorithm, I hope knowledgeable downloaded to look for a simple description of the Chinese!)
- 2020-10-19 21:37:25下载
- 积分：1
