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sim_uart
uart 收发器 verilog 代码,实现自收发功能
sys clk = 25m, baud 9600 停止位1, 无校验位;
代码实现了串口自收发功能,及把从 PC 收到的内容都发送会 PC, 其他波特率,自行修改代码即可,在 alter 的FPGA 上调试通过;
(verilog code uart transceiver to achieve self-transceiver function sys clk = 25m, baud 9600 1 stop bit, no parity code from the transceiver features a serial port, and the contents received from the PC will send the PC, another Potter rate, self-modifying code can, in the alter of the FPGA, debugging through )
- 2010-10-10 21:49:46下载
- 积分:1
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verilog uart 115200
使用verilog编写的串口uart发送模块,发送速率为115200,输入时钟为50m,多年验证无任何错误
- 2022-02-09 17:35:29下载
- 积分:1
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EEPROM_RD_WR
本程序包含:EEPROM的功能模型(eeprom.v)、读/写EEPROM的verilog HDL 行为模块(eeprom_wr.v)、信号产生模块(signal.v)和顶层模块(top.v) ,这样可以有一个完整的EEPROM的控制模块和测试文件,本文件通过测试。(This procedure includes: EEPROM of the functional model (eeprom.v), read/write EEPROM acts of verilog HDL modules (eeprom_wr.v), signal generator module (signal.v) and top-level module (top.v), this can have a EEPROM complete control module and test document, this document is to pass the test.)
- 2008-12-23 15:04:20下载
- 积分:1
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FPGA_Seg7_dsp
关于VHDL和verilog的数码管显示程序,写的很好,值得参考。(About VHDL and verilog digital tube display program, write well, worth considering.)
- 2014-08-01 11:00:51下载
- 积分:1
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banjian
完成一个1位全减器的设计。以全减器为元件程序完成8位减法器设计。(Completed a one minus the whole design. Full reduction is to complete eight subtraction element program design.)
- 2015-06-26 21:17:49下载
- 积分:1
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此代码为使用SPI 28335 ad9959
此代码为使用SPI
用于实现28335控制AD9959输出信号的频率、幅度(This code uses SPI
The Frequency and Amplitude of AD9959 Output Signal Controlled by 28335)
- 2020-06-24 02:00:02下载
- 积分:1
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DDC
verilog语言实现的数字下变频设计。
在ALTERA的QUARTUS ii下实现。实用,好用。(Verilog language implementation of the digital down-conversion design. ALTERA at the implementation of QUARTUS ii. Practical, easy to use.)
- 2009-03-23 20:42:56下载
- 积分:1
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ahb_sramc
基于AHB总线的sram控制器,带有memory bist(SRAM controller based on AHB bus)
- 2018-05-19 20:47:28下载
- 积分:1
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MultiMIPS
多周期MIPS system vivado实现(Multi-cycle MIPS system vivado)
- 2018-06-24 18:19:29下载
- 积分:1
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键盘按键消抖
键盘按键消抖,短时间内的摁键键值采集,在规定时间内,如果存在按键的上升沿和下降沿,不予以采集,超过该时间,则采集为该键当前状态值
- 2022-08-10 06:33:27下载
- 积分:1