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完成的是RS422信号的计数功能，并产生一定的触发信号
完成的是RS422信号的计数功能，并产生一定的触发信号-RS422 signals the completion of the count function, and produce a certain trigger signals
- 2022-04-14 14:08:50下载
- 积分：1
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vending-machine
用Verilog实现自动售货机功能，代码较初级。易懂，内含test文件。(Automatic vending machines function with Verilog code than the primary. Understandable, containing test files.)
- 2013-11-30 20:25:34下载
- 积分：1
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fpga超声波测距
FPGA开发超声波测距，可改写工业探伤或倒车测距等系统，quartus2下选择EP2C5Q208C8（CycloneⅡ） 支持目前淘宝上能买到的所有4-5针超声波模块 应用cycloneⅡ自带除法模块 开发板为有光技术YG2.1 生成电路规模较小 ！！注意：移植程序仅需重新约束数码管和超声波模块的针脚
(Ultrasonic Ranging FPGA development, industrial inspection or reverse rewritable ranging systems, EP2C5Q208C8 (CycloneⅡ) under quartus2 4-5 needle ultrasonic module supports all currently scouring the treasure can buy Applications cycloneⅡ own division module Development board bright technical YG2.1 Small scale generating circuit ! ! Note: The migration program only re-constraint digital and ultrasonic modules Pin)
- 2022-07-17 19:43:35下载
- 积分：1
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本书是一本Verilog语言设计和综合手册,对学习Verilog语言有很大作用,值得阅读....
本书是一本Verilog语言设计和综合手册,对学习Verilog语言有很大作用,值得阅读.
- 2023-03-07 07:25:03下载
- 积分：1
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2MW_wind_grid_inverter
针对兆瓦级风电并网逆变器主电路研制中存在的并联扩容、开关频率较低和LCL滤波器难以优化设计等问题，提出了采用交流侧串接电感再进行并联的均流方案，采用载波移相技术提高变流器的等效开关频率，提出了LCL滤波器的设计原则，并给出了上述设计的理论依据和实现方法。通过对2兆瓦风电变流器主电路的仿真验证了上述技术方案。(MW-class wind power for grid-inverter main circuit of the parallel development of existing capacity, a lower switching frequency and LCL filter design difficult to optimize the problem, a series inductor AC side in parallel are further flow program, the use of carrier phase-shifting technology to enhance the equivalent converter switching frequency, a LCL filter design principles, and gives the above-mentioned theoretical basis for the design and implementation. 2 MW of wind power converter main circuit simulation program to verify the above-mentioned technology.)
- 2009-04-28 09:16:38下载
- 积分：1
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ahb 总线协议
本文以 VHDL 语言编码得到了 AMBA 与 AHB 总线仲裁。这里在本文中，我们设计了 AMBA 总线协议，将用于多奴隶通信环境，多主
- 2022-01-25 21:18:17下载
- 积分：1
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codes
EKG SIGNAL PROCESSING THROUGH CORDIC
- 2013-09-29 01:46:17下载
- 积分：1
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TRY-1516-CSV0115--- SANGEETHA
VHDL BASED DATA COMPRESSION
- 2019-01-01 16:37:53下载
- 积分：1
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gobang
一个用verilog实现的五子棋程序，用在fpga上，连接显示器，可选择与电脑对战或是双人对战，按wsad控制方向，回车控制落子，程序会自动判断输赢并显示结果(A 331 procedures implemented by verilog, used in fpga, connect the monitor, you can choose to play against the computer or a double play, press wsad control the direction, carriage control Lazi, the program will automatically determine the winners and losers and display the results)
- 2015-03-30 13:13:35下载
- 积分：1
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VHDL与源代码包
VHDL与源代码包-and VHDL source code
- 2022-02-03 22:44:25下载
- 积分：1
