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VGA_Test
说明： 基于FPGA的VGA驱动代码VHDL
在显示屏显示一个汉字(FPGA-based VHDL code of the VGA driver that a character in the display)
- 2009-08-10 14:55:27下载
- 积分：1
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ddr3control
8位突发长度，一次64bit数据读写，MIG核(DDR3 controll implimention)
- 2021-05-07 13:58:36下载
- 积分：1
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CD1_PHOTO_ABLUM_1920
使用FPGA做的数码相册实验，用NIOS做了FAT32文件系统和JPEG图像解码,FPGA和SDRAM做了显示的缓存(Using FPGA to do the digital album experiment, using NIOS to do the FAT32 file system and JPEG image decoding, FPGA and SDRAM to do the display cache)
- 2016-07-13 10:04:56下载
- 积分：1
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RS-422standardmodulev2
rs422标准通讯模块 异步收发 verilog语言编写(rs422 standard communication module asynchronous receiver verilog language)
- 2013-12-23 14:14:18下载
- 积分：1
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h_adder
ise13.2环境下VHDL编写的半加器器+仿真波形(ise13.2 environment half adder in VHDL simulation waveform control+)
- 2013-06-01 13:40:03下载
- 积分：1
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MAC
在FPGA硬件上，使用verilog语言编写的一个乘累加器程序。(FPGA hardware, a multiply accumulator verilog language program.)
- 2012-10-18 20:28:25下载
- 积分：1
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verilog hdl coding DDR sdram control for fpga
verilog hdl coding DDR sdram control for fpga -verilog hdl coding DDR sdram control for fpga
- 2022-03-23 21:20:26下载
- 积分：1
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BoneMicoren
Bone microphnoe simulator.
this is a trial to de-noise the bone microphone signals.
This also utilizes om-lsa algorithm
- 2012-12-12 04:47:28下载
- 积分：1
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Detailed description of the FPGA design flow of the entire FPGA design flow full...
详细的说明了FPGA设计的整个流程
FPGA设计全流程Modelsim>>Synplify.Pro>>ISE-Detailed description of the FPGA design flow of the entire FPGA design flow full Modelsim> > Synplify.Pro> > ISE
- 2022-11-01 22:10:02下载
- 积分：1
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UML_2_Pour_les_bases_de_donnees
UML2 apprendre a modeliser a l aide de UML
- 2014-02-25 01:32:23下载
- 积分：1
