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一个简单的曼彻斯特编码器,将串行数据转换为曼彻斯特编码数据。
A simple Manchester Encoder to convert serial data to Manchester encoded data.
- 2022-06-20 14:27:09下载
- 积分:1
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last
verilog,FPGA的TDC电路设计(verilog ,TDC base on FPGA)
- 2021-01-04 18:48:54下载
- 积分:1
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VHDL编写的4个led灯循环明暗变化,通过改变波形占空比实现,课堂作业自编程序...
VHDL编写的4个led灯循环明暗变化,通过改变波形占空比实现,课堂作业自编程序-VHDL prepared by the four led lights cycle shading changes, by changing the waveform duty cycle to achieve, self-compiled class operating procedures
- 2022-04-17 17:16:20下载
- 积分:1
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Three-Pulse-VSR-
对三相电压型逆变器的数学模型进行了详细的数学推导,简单容易理解(Three-phase voltage inverter for the mathematical model of a detailed mathematical derivation is simple and easy to understand)
- 2011-08-14 22:30:28下载
- 积分:1
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Digital Cymometer VHDL procedures and simulation of the file name: plj.vhd.
数字频率计VHDL程序与仿真
文件名:plj.vhd。
--功能:频率计。具有4位显示,能自动根据7位十进制计数的结果,自动选择有效数据的
--高4位进行动态显示。小数点表示是千位,即KHz。
-Digital Cymometer VHDL procedures and simulation of the file name: plj.vhd.- Function: frequency meter. With four shows that will automatically count seven decimal results, automatic selection of effective data- four for the high dynamic display. Decimal point that is 1000, or KHz.
- 2022-08-04 07:22:59下载
- 积分:1
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juanji
FPGA的卷积编码小程序,VHDL描述,参数为2,1,7.(2,1,7 cov with VHDL.)
- 2010-09-24 20:28:22下载
- 积分:1
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Block-cipher-lock
密码锁verilog源代码,包括四个七段数码管显示模块,设置密码以及输入密码校验模块(Password lock Verilog source code, including four of seven digital tube display module, set the password and password verification module)
- 2014-01-11 23:57:19下载
- 积分:1
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Copy-of-DIGITAL-VLSI-DESIGN
a manual for design implementation of fpga and ASIC using verilog
- 2012-09-04 17:34:58下载
- 积分:1
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3.1.19-GEC2410_LCD_HZ
嵌入式的LCD的图片显示程序,是LCD最好的资料。(Embedded LCD picture display program is the best LCD data.)
- 2013-06-15 15:57:40下载
- 积分:1
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VerilogHDL.自动增益控制模块中产生控制电压的部分
VerilogHDL.自动增益控制模块中产生控制电压的部分-VerilogHDL. Automatic Gain Control Module have some control voltage
- 2022-06-19 20:17:38下载
- 积分:1