登录
首页 » VHDL » 译码器,将八位输出转换为七段译码显示,相当于7448驱动译码管...

译码器,将八位输出转换为七段译码显示,相当于7448驱动译码管...

于 2022-05-30 发布 文件大小:4.62 kB
0 160
下载积分: 2 下载次数: 1

代码说明:

译码器,将八位输出转换为七段译码显示,相当于7448驱动译码管-Decoder, the 8 output is converted to seven segment decoding shows that the equivalent of 7448

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • I2C_master_code
    主要介绍,I2C总线主设备发送数据给从设备,代码实现是用Verilog语言实现的,对硬件设计者有很大好处(Introduces, I2C bus master to send data to the slave device, code is implemented in Verilog language, the hardware designer of great benefit)
    2011-07-12 14:31:11下载
    积分:1
  • xilinx simulator programme of serial port
    xilinx的串口仿真程序-xilinx simulator programme of serial port
    2022-11-08 03:05:05下载
    积分:1
  • VHDL language learning paradigm, the FSK
    学习VHDL语言的范例,有关FSK-VHDL language learning paradigm, the FSK
    2023-06-01 13:25:03下载
    积分:1
  • apb timer
    说明:  是基于apb总线下的timer外设的rtl代码,主要包括apb_timer的master逻辑verilog,以及相应的开发文档,包括寄存器的描述,功能特性等。(RTL code is based on timer peripheral under APB bus, which mainly includes master logic Verilog of apb_timer and corresponding development documents, including the description of registers, functional characteristics and so on.)
    2019-01-25 16:54:02下载
    积分:1
  • verilog写的数字频率计的控制模块,对程序进行控制
    verilog写的数字频率计的控制模块,对程序进行控制-written in Verilog digital frequency meter control module, the program control
    2022-02-04 00:52:27下载
    积分:1
  • clkdiv
    基于Verilog的FPGA时钟分频程序(FPGA clock frequency division program based on Verilog)
    2018-06-10 17:08:57下载
    积分:1
  • TrackMe
    人的移动的跟踪,VERILOG实现,能跟踪人的画面移动(Tracking the movement of people, VERILOG realize that can track the person)
    2021-04-29 15:48:43下载
    积分:1
  • High Speed dd
    (Springer Series in Advanced Microelectronics 51) Ayan Palchaudhuri, Rajat Subhra Chakraborty (auth.)-High Performance Integer Arithmetic Circuit Design on FPGA_ Architecture, Implementation and Desig
    2020-06-24 08:40:01下载
    积分:1
  • 1
    一个解决除法溢出的例子,可以学习到很多,注释很详细(A solution to the division overflow example, you can learn a lot, very detailed notes)
    2013-12-24 09:19:13下载
    积分:1
  • 是verilog例子。初级适用。包括了简单的例子。
    是verilog例子。初级适用。包括了简单的例子。-example. The initial application. Including a simple example.
    2022-05-31 23:36:48下载
    积分:1
  • 696516资源总数
  • 106571会员总数
  • 2今日下载