-
用VHDL编写的EPP通信协议，可以同时收发字节
用VHDL编写的EPP通信协议，可以同时收发字节-EPP written in VHDL, communication protocol, you can also send and receive bytes
- 2022-05-22 02:38:48下载
- 积分：1
-
useful
FPGA做VGA视频显示的详细资料，我找了很久才收集起的，有四篇文章，很有用(FPGA do VGA video display detailed information, I found a long time before they start collecting, with four articles, very useful)
- 2020-12-21 18:29:09下载
- 积分：1
-
超大规模集成电路的VHDL基本编码…………
- 2022-03-26 19:32:17下载
- 积分：1
-
06219426Spartan3E
VHDL汇编语言原理及源代码。spartan 3e开发板试用。(VHDL language.)
- 2011-02-10 09:41:12下载
- 积分：1
-
VHDL ip core的设计，软核的设计方法
VHDL ip core的设计，软核的设计方法-VHDL core of the design, soft-core design
- 2022-06-01 06:05:02下载
- 积分：1
-
osiclator LED
应用背景弗鲁托PA oscilar就像联合国领导是卡瓦依，zholo罗该为什么我需要一个接着一个普通该estudielo为什么deberia darselo masticado关键技术zh0lo VHDL l0ks，就像PA presumir Y阙我书房一个接着一个普通免费，但四sintetiza Y有她comportamiento寺特拉华入伍机构sincronizar O把一osiclar DOS LED
- 2022-11-27 18:40:03下载
- 积分：1
-
Multi_function
01 线性调频信号的卷积功能测试（匹配）
02 LFM一维距离像
03 MATLAB联合FPGA仿真输入/输出功能测试
04 解速度模糊
05 扩展目标检测(01 LFM Test function of "conv"
02 LFM Range
03 MATLAB and FPGA
04 resovle speed resolution
05 Extended moving target)
- 2013-05-03 15:53:43下载
- 积分：1
-
FPGA-timing-constraints
基于Verilog的FPGA设计时序分析约束详细解释与使用方法(FPGA timing constraints)
- 2017-04-24 09:54:35下载
- 积分：1
-
verilog-ethernet
说明： Collection of Ethernet-related components for gigabit, 10G, and 25G packet processing (8 bit and 64 bit datapaths). Includes modules for handling Ethernet frames as well as IP, UDP, and ARP and the components for constructing a complete UDP/IP stack. Includes MAC modules for gigabit and 10G/25G, a 10G/25G PCS/PMA PHY module, and a 10G/25G combination MAC/PCS/PMA module. Includes various PTP related components for implementing systems that require precise time synchronization. Also includes full MyHDL testbench with intelligent bus cosimulation endpoints.
- 2021-04-17 23:38:52下载
- 积分：1
-
这是FPGA的Spartan 3E基础工程文件。该项目是基于VGA游戏…
this fpga spartan 3e based project file .the project is the game based on vga.
this file contains 2,20,25,400Hz clock generating file as per required for the project.-this is fpga spartan 3e based project file .the project is the game based on vga.
this file contains 2,20,25,400Hz clock generating file as per required for the project.
- 2023-02-25 10:20:03下载
- 积分：1
