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lab7_files
关于Digilent Atlys Spartan-6 FPGA development board audio ac97的讲解及具体应用的源码(Digilent Atlys Spartan-6 FPGA development board audio of ac97' s presentation as well as the specific application' s source code)
- 2013-02-01 11:02:38下载
- 积分：1
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2
说明： Objects forming possible solution within original problem context are called phenotypes, their encoding, the individuals within the GA, are called genotypes.
The representation step specifies the mapping the phenotypes onto a set of genotypes.
Candidate solution, phenotype and individual are used to denotes points of the space of possible solutions. This space is called phenotype space.
Chromosome, and individual can be used for points in the genotye space.
Elements of a chromosome are called genes. A value of a gene is called an allele.
Variation Operators
The role of variation operators is to create new individuals old ones. Variation operators form the implementation of the elementary steps with the search space.
- 2014-12-22 22:54:47下载
- 积分：1
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CORDIC 代码
说明： Xilinx CORDIC 算法 MATLAB Verilog仿真(arctan.m Kn.m sin_cos.m MATLAB Verilog)
- 2019-03-27 09:53:35下载
- 积分：1
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很多实用的例程，包括触发器，译码器，多路选择器
很多实用的例程，包括触发器，译码器，多路选择器-A lot of useful routines, including the flip-flop, decoder, MUX
- 2022-03-06 03:11:07下载
- 积分：1
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Farrow-filter-design
两篇中文论文，详细叙述了Farrow滤波器的设计方式和理论基础，非常实用！(Two Chinese papers, described in detail Farrow filter design methods and theoretical foundation, very useful!)
- 2013-11-15 17:15:20下载
- 积分：1
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//led.v
/*
//led.v
/*-------------------------------------
LED显示模块：led(CLK,AF,ADDR,DATA)
功能： 显示
注意事项： 8位LED
参数： CLK:扫妙时钟输入，推荐1kHz
AF:数码管输出，a～h
ADDR:数码管选择位数出，0~2
DATA:显示数据输入0~9999 9999
编写人： 黄道斌
编写日期： 2006/07/13
-------------------------------------*/-//led.v /*------------------------------------- LED Display Module : led (CLK, AF, ADDR. DATA) function : to show : 8 LED parameters : CLK : So Wonderful clock input, Suggest 1kHz AF : digital tube output, a ~ h ADDR : digital control options from the median, 0 ~ 2 DATA : data show that the importation of 0 ~ 9999 9999 prepared : Huang Daobin preparation date : 2006/07/13-------------------------------------*/
- 2022-06-03 00:26:09下载
- 积分：1
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本代码实现了全加器功能，适合初学者学习
本代码实现了全加器的功能，可供初学者学习-This code implements a full adder functions, for beginners to learn
- 2022-03-09 20:15:10下载
- 积分：1
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veye_mipi
说明： 1、 例程功能VEYE-290-LVDS模组视频接入演示。（显示设备必须支持1080p/30或1080p/25的帧率）
Veye模组—>MIA701开发板—>HDMI显示设备
2、 本例程硬件平台
MIA701-PCIE开发板，FPGA芯片：XC7A100TFGG484
3、 软件平台Vivado2018.1。
4、 附件含开发板原理图（底板+核心板）(1. Video access demonstration of routine function VEYE-290-LVDS module. (Display devices must support 1080p/30 or 1080p/25 frame rates) Veye Module - > MIA701 Development Board - > HDMI Display Equipment 2. The hardware platform of this routine MIA701-PCIE development board, FPGA chip: XC7A100TFG484 3. Software platform Vivado 2018.1. 4. Appendix contains schematic diagram of development board (bottom + core board))
- 2019-04-01 11:08:04下载
- 积分：1
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dec2_4
decoder 2-4
digital core
- 2016-05-20 03:50:28下载
- 积分：1
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h264_intp
图形图像H264插值算法，应用于图像视频处理(H264 graphic image interpolation algorithm is applied to image video processing)
- 2021-05-14 18:30:02下载
- 积分：1
