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VHDL数字频率计（1）频率测量范围： 10 ～ 9999Hz 。
（2）输入电压幅度 >300mV 。
（3）输入信号波形：任意周期信号。...
VHDL数字频率计（1）频率测量范围： 10 ～ 9999Hz 。
（2）输入电压幅度 >300mV 。
（3）输入信号波形：任意周期信号。
（4）显示位数： 4 位。
（5）电源： 220V 、 50Hz
-vhdl
- 2022-07-20 20:49:22下载
- 积分：1
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homework32
说明： 这是32位移位寄存器，是用verilog编写的，能够实现从1到31位的左或右的移位(This is a 32-bit shift register, is prepared verilog, can be realized from the 1-31 shift left or right)
- 2009-07-27 15:54:00下载
- 积分：1
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shuzishizhong
数字时钟，包括流程图以及编码和完整的实验报告，内容详细丰富。(Digital clock, including flowcharts, and coding and a full lab report, detailed and rich.)
- 2011-12-20 19:53:07下载
- 积分：1
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zzlB
QUARTUSII 9.0 下的三级流水线中值滤波工程，vhdl源程序等。可用于fpga做图像预处理。(the three stage pipeline median filter project under QUARTUSII 9 , VHDL source program. which can be used by FPGA to do image preprocessing.
)
- 2011-12-21 16:17:41下载
- 积分：1
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webserver_c3
The term web server can refer to either the hardware (the computer) or the software (the computer application) that helps to deliver web content that can be accessed through the Internet.(web server)
- 2014-03-23 20:00:14下载
- 积分：1
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myDPll
说明： 本人写的数字锁相环，有模拟数据，学习锁相环很好的材料。参考书“数字锁相环路原理与应用”编写。(I write the digital phase-locked loop, have simulated data, a good phase-locked loop learning materials. Reference book )
- 2008-08-29 08:54:53下载
- 积分：1
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bandpass
FIR有限冲击响应下带通滤波器的构建及滤波器仿真（通过matlab和simulink两种方法实现）(FIR finite impulse response bandpass filter and filter simulation (via two methods matlab and simulink))
- 2013-03-13 18:32:07下载
- 积分：1
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-Elliptic
We present elliptic curve cryptography (ECC) coprocessor,
which is dual-field processor with projective
coordinator. We have implemented architecture for scalar
multiplication, which is key operation in elliptic curve
cryptography. Our coprocessor can be adapted both prime field
and binary field, also contains a control unit with 256 bit serial
and parallel operations , which provide integrated highthroughput
with low power consumptions. Our scalar multiplier
architecture operation is perform base on clock rate and produce
better performance in term of time and area compared to similar
works. We used Verilog for programming and synthesized using
Xilinx Vertex II Pro devices. Simulation was done with Modelsim
XE 6.1e, VLSI simulation software from Mentor Graphics
Corporation especially for Xilinx devices.
- 2012-02-09 10:48:50下载
- 积分：1
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dds32_1
说明： 频率合成器实例模块设计。频率分辨率为32位DDS的VHDL程序(Frequency synthesizer module design example. 32-bit DDS frequency resolution of the VHDL program)
- 2011-04-14 13:45:22下载
- 积分：1
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5.c
; for 16-bit app support
[386Enh]
woafont=dosapp.fon
EGA80WOA.FON=EGA80WOA.FON
EGA40WOA.FON=EGA40WOA.FON
CGA80WOA.FON=CGA80WOA.FON
CGA40WOA.FON=CGA40WOA.FON
- 2017-11-07 04:17:08下载
- 积分：1
