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Dodge_block
说明： 用Verilog实现的基于FPGA的简单避障游戏(A game based on FPGA,using Verilog)
- 2020-07-29 22:38:39下载
- 积分：1
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091655
基于fpga的coms摄像头
扫描，参考文献，(Fpga based on the coms camera scan, reference literature,)
- 2010-08-09 01:03:12下载
- 积分：1
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steper motor
说明： stepper motor module on spartan 6 and 24MHz clock fequency
- 2019-03-10 15:44:31下载
- 积分：1
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PWM
飞思卡尔智能车芯片模块程序 MC9S12XS128 测试通过(freescale smart car for MC9S12XS128)
- 2011-08-04 10:34:33下载
- 积分：1
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gtx
ip core of the transceiver gtx
- 2019-04-02 00:10:03下载
- 积分：1
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DLX-pipeline-in-verilog
verilog实现DLX指令集5段流水线(5 stage DLX pipeline implemented in verilog)
- 2013-08-24 22:59:48下载
- 积分：1
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c8051fPLL
说明： C8051F的一个特点就是可以倍频到100M。近来用到。在单片机的调试通过其PLL倍频函数。供用到的朋友参考和借鉴。(One feature is the ability C8051F multiplier to 100M. Recently used. In MCU debugging functions through its PLL multiplier. Used for reference for a friend.)
- 2021-03-04 12:39:32下载
- 积分：1
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BGM benchmark
// DEFINES
`define BITS 32 // Bit width of the operands
`define NumPath 34
module bgm(clock,
reset,
sigma_a,
sigma_b,
sigma_c,
Fn,
dw_x,
dw_y,
dw_z,
dt,
Fn_out
);
// SIGNAL DECLARATIONS
input clock;
input reset;
input [`BITS-1:0] sigma_a;
input [`BITS-1:0] sigma_b;
input [`BITS-1:0] sigma_c;
input [`BITS-1:0] Fn;
input [`BITS-1:0] dw_x;
input [`BITS-1:0] dw_y;
input [`BITS-1:0] dw_z;
input [`BITS-1:0] dt;
- 2022-04-09 23:29:23下载
- 积分：1
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OQPSK_fading
OQPSK在AWGN和频率选择性衰落信道中的仿真(OQPSK the AWGN and frequency selective fading channel simulation)
- 2021-04-05 21:49:03下载
- 积分：1
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volt_mea_disp
本程序是用verilog 编写的模块，用来在lcd1602上显示用tlc549采样的电压值(This program is written in verilog module, used in lcd1602 display with tlc549 sampled voltage value)
- 2013-07-26 00:58:35下载
- 积分：1
