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FPGA 逻辑分析仪
quartus verilog 逻辑分析仪, 检测数字信号(与示波器检测模拟信号对应),vga显示输出。经过本人调试可用。
- 2022-02-13 05:11:50下载
- 积分:1
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CycloneII_NiosII_2C35_Rev02_DB_SCH
说明: nios开发板电路图CycloneII_NiosII_2C35_Rev02_DB_SCH.zip(nios development board circuit CycloneII_NiosII_2C35_Rev02_DB_SCH.zip)
- 2010-03-28 20:50:27下载
- 积分:1
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v-watch
基于fpga的数字电压表的设计,包括ad转换,bcd码转换,分频,3选1模块,小数点生成模块,显示模块组成。(Based on the FPGA digital voltage meter design, including AD conversion, BCD code conversion, frequency,3 choose1module, a decimal point generating module, display module.
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- 2012-05-10 01:29:23下载
- 积分:1
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ddr3 sdram 控制器代码,verilog
根据DDR3的特点和操作原理,利用MIG软件工具在Virtex-6系列FPGA中实现DDR3SDRAM控制器的设计,并给出了硬件测试的结果,代码为verilog,通过仲裁机制完成设计,希望对学习fpga的人有帮助
- 2022-07-09 17:26:37下载
- 积分:1
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DS18B20
DS18B20温度传感器的基于FPGA的编程通信,使用VHDL语言(DS18B20 temperature sensor based FPGA programming communication with VHDL)
- 2012-07-16 19:10:29下载
- 积分:1
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sdram_epm570_uart
基于CPLD芯片EPM570的verilog hdl串口程序(the UART verilog hdl code based on CPLD chip-- EPM570)
- 2014-06-03 20:27:45下载
- 积分:1
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RS232通用代码
常用的rs232代码,可直接调用,也可以适当修改参数,默认115200波特率
- 2022-06-16 11:27:07下载
- 积分:1
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VCS使用中文教程
说明: vcs中文使用教程,帮助你快速入门Linux下的VCS操作(VCs Chinese tutorial to help you get started with VCs operation under Linux)
- 2020-07-01 23:00:02下载
- 积分:1
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imports
说明: displayport 参考设计,可以对比自己工程做验证,另有参考设计XAPP1178未找到,采用方案为DP159 + Artix7 FPGA(xilinx displayport sink design)
- 2021-01-11 16:58:50下载
- 积分:1
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phone
用DE0开发板实现电话计费器,基本功能:可设置通话模式,能初始化话费余额,拨动开关可进入通话模式,并根据通话时间和相应通话模式扣除相应的费用。通话过程中能够通过开关切换显示通话时间和话费余额,并可暂停通话。压缩包里有详细的WORD文档的说明,包括波形仿真和DE0的引脚功能介绍。(Implemented by DE0 board telephone billing, basic function: to set the call mode, you can initiate credit balance, toggle switch into the talk mode, and deduct the cost of a call based on call time and the corresponding mode. Call talk time and can be displayed by switching credit balance, and mute. Compression bag has a detailed description of WORD documents, including the waveform simulation and DE0 pin function description.)
- 2020-11-06 13:19:49下载
- 积分:1