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PCIe_Lab(ALTERA-V5PCIe)
这一设计实例深入浅出，介绍怎样产生一个Qsys子系统。 您将产生一个含有以下组成的Qsys系统:在Cyclone IV GX收发器入门套件上,设计带嵌入式收发器的Gen1×1硬核IP的 PCI Express IP编译器。
(Qsys system: the Cyclone IV GX Transceiver Starter Kit, designed with embedded transceivers Gen1 × 1 hard IP PCI Express IP compiler.)
- 2020-12-02 18:39:25下载
- 积分：1
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数字信号处理的FPGA实现(第4版)源码
数字信号处理的FPGA实现(第4版)的配套源码，极具参考价值。(The source code of the realization of digital signal processing on FPGA (4th edition) is of great reference value.)
- 2021-01-16 23:08:50下载
- 积分：1
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Xilinx vivado authoritative course
Xilinx vivado 权威教程，清华大学出版社出版，何宾编著。(Xilinx vivado authoritative course, published by Tsinghua University Press, edited by He Bin.)
- 2019-02-19 20:37:09下载
- 积分：1
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csbar(3) : X"E0000" to X"E01FF"
-- M68008 Address Decoder
-- Address decoder for the m68008
-- asbar must be 0 to enable any output
-- csbar(0) : X"00000" to X"01FFF"
-- csbar(1) : X"40000" to X"43FFF"
-- csbar(2) : X"08000" to X"0AFFF"
-- csbar(3) : X"E0000" to X"E01FF"
-- download from www.pld.com.cn & www.fpga.com.cn
--- M68008 Address Decoder-- Address decod er for the m68008-- 0 asbar must be to enable any o utput-- csbar (0) : X "00000" to X "01FFF"-- csbar (1) : X "40000" to X "43FFF"-- csbar (2) : X "08000" to X "0AFFF"-- csbar (3) : X "E0000" to X "E01FF"-- download from www.pld. com.cn
- 2022-02-26 21:53:57下载
- 积分：1
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performance with rayleigh
matlab bpsk with rayleigh performance expirement
- 2020-06-24 21:40:01下载
- 积分：1
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Digital signal source, the output of different frequency, phase is the cosine si...
数字信号源，输出不同频率，相位的正余弦信号，-Digital signal source, the output of different frequency, phase is the cosine signal,
- 2022-04-23 09:40:37下载
- 积分：1
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Altera公司的NIOSⅡ处理器，VHDL语言编译，然后在C语言下的nios……
ALTERA NIOS处理器，VHDL语言在QUARTUS编译通过，然后有C语言在NIOS SHELL下驱动，实验音频解码-Altera NIOS processor, the QUARTUS VHDL compiler, then the C language under NIOS SHELL-driven, experimental audio decoder
- 2022-03-21 08:10:03下载
- 积分：1
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Building and Using Counters - DE2-115
本练习的目的是构建和使用计数器。所设计的电路将在计算机上实现
- 2022-03-25 20:38:37下载
- 积分：1
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Verilog-learning-experience
初学学习verilog的经验，可以帮助新手以正确的思维方式，学习方法学习。(Verilog learning experience)
- 2013-09-30 09:51:04下载
- 积分：1
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Voltage pulse control of a project
电压脉冲控制的一个工程---包括vhdl源程序和编译后产生的相关文件-Voltage pulse control of a project- including VHDL source code and compile the relevant documents after
- 2022-03-20 09:09:15下载
- 积分：1
