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lcd_system
LCD显示工程，其中包含了顶层文件和各个底层文件(LCD display project, which contains the top-level document and all underlying file)
- 2013-07-24 08:58:53下载
- 积分：1
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SPI_test
用FPGA于32进行SPI单向通信，FPGA向32放松发送数据(One-way SPI communication is carried out in 32 with FPGA, and data is sent to 32 with ease by FPGA.)
- 2020-06-18 10:40:02下载
- 积分：1
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mini_cpu_verilog
用verilog写的简单的CPU，有详细注释(Use verilog to write a simple CPU, with detailed notes)
- 2011-07-16 09:20:27下载
- 积分：1
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verilog_DATA_displays
使用verilog语言，滚动显示“verilog”字符串程序代码及相关说明(Using verilog language, scrolling display " verilog" string code and instructions)
- 2014-01-16 10:49:55下载
- 积分：1
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complex_timing_by_Primetime
用PrimeTime的技巧，解决复杂时钟问题。(The world of telecommunications chips is full of messy clocking situations. This paper will cover the tricks and tehniques that author Paul Zimmer has developed to avoid the need to pour over reams of timing reports looking for problems. Best paper winner at SNUG San Jose 2001!)
- 2012-08-05 19:07:47下载
- 积分：1
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MIPSTOP
说明： misp顶层文件，verilog实现misp架构，并且支持modelsim仿真(Verilog implements MISP architecture and supports Modelsim simulation)
- 2020-06-18 04:40:02下载
- 积分：1
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vhdl_codes
D-flip flop vhdl implement code
- 2012-04-13 14:03:13下载
- 积分：1
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ADC0832TLC5615
开关电源中用单片机产生可调电压控制PWM波程序,ADC0832读取输出电压(Single-chip switching power supply using adjustable voltage control PWM wave generation process, ADC0832 read the output voltage)
- 2011-09-16 23:37:27下载
- 积分：1
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sph-original-codes
SPH的原始代码，希望可以帮到大家啊关于模拟poiseuille的(simulate poiseuille fuild)
- 2020-10-22 10:27:23下载
- 积分：1
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DDR3_user_design
在Xilinx开发环境ISE13.2上用MIG产生的DDR3 SDRAM控制器，里面生成了Core，可用于DDR3读写控制(On the Xilinx development environment ISE13.2 generated with MIG DDR3 SDRAM controller, which generates the Core, DDR3 can be used to read and write control)
- 2012-02-02 15:16:00下载
- 积分：1
