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filter-design
MBD-FPGA数字滤波器设计基本流程,基于DSP builder(MBD-FPGA basic process of digital filter design)
- 2020-12-02 20:39:26下载
- 积分:1
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1_Carm
经典的OV5642的verilog驱动程序(Verilog Driver of Classic OV5642)
- 2019-03-19 13:38:29下载
- 积分:1
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UART_RX_
fpga串口的发送程序基于verilog语言拿走不用谢。(The sending program of FPGA serial port is based on Verilog language.)
- 2020-06-18 04:00:01下载
- 积分:1
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8832135
一个具有“百分秒,秒,分”计时功能的数字跑表,可以实现一个小时以内的精确至百分之一秒的计时。
数字跑表的显示读者可以通过编写数码管显示程序来实现,本训练只给出数字跑表的实现过程。
读者还可以通过增加小时的计时功能,实现完整的跑表功能。(A " percentage of seconds, seconds, minutes," digital stopwatch timer can be achieved within an hour of precision to the hundredth of a second time. Digital stopwatch readers can display the digital display through the preparation of procedures to achieve, given the training is only the realization of the process of digital stopwatch. Readers can also function to increase hours of time to achieve full stopwatch function.)
- 2009-04-09 13:20:35下载
- 积分:1
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10进制的FPGA数字计数器
本程序可以在DE1-SOC的实现10进制的FPGA数字计数器
- 2023-07-19 19:25:05下载
- 积分:1
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1
说明: 一个解决除法溢出的例子,可以学习到很多,注释很详细(A solution to the division overflow example, you can learn a lot, very detailed notes)
- 2013-12-24 09:19:13下载
- 积分:1
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halfband
verilog写的39阶通带为20KHz的半带fir滤波器,经测试正确。(verilog halfband FIR)
- 2020-12-25 14:29:04下载
- 积分:1
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PS2_verilog基于ps2的接口,对于刚接触FPGA是个很好的选择
PS2_verilog基于ps2的接口,对于刚接触FPGA是个很好的选择,PS2_verilog基于ps2的接口,对于刚接触FPGA是个很好的选择
- 2022-02-20 06:07:15下载
- 积分:1
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DPD_project
预失真算法中,包络解波部分的verilog代码,有部分错误(envelope calculation of DPD algorithm ,verilong HDL language)
- 2014-04-26 15:45:21下载
- 积分:1
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shuzizhong3
数字钟VHDL软件设计,包含多种功能,报时,12,24切换,调时(The design of VHDL digital clock software, including a variety of functions, timer, 12,24 switch, adjustable)
- 2016-05-27 11:41:22下载
- 积分:1