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一个实用的verilog除法器
这是一个可综合的除法器,内部包含除法模块,比较模块,除法模块。
- 2022-05-16 15:39:39下载
- 积分:1
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HDB3
用Verilog HDL语言进行HDB3编码,并通过Quartus Ⅱ仿真验证(With the Verilog HDL language HDB3 coding, and simulation by Quartus Ⅱ)
- 2020-11-30 11:19:28下载
- 积分:1
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uart code dsdlab with my clock code
uart代码dsdlab与我的时钟代码.it是一个用于实现uart设计的verilog代码代码。这个是数字系统设计实验室的实践。
- 2022-09-14 16:00:03下载
- 积分:1
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divf_even
基于FPGA cyclone2的偶数分频模块,可实现自定义分频数(Based on FPGA cyclone2
even number of frequency divider module, custom frequency divider can be realized.)
- 2018-11-06 12:11:46下载
- 积分:1
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13.2_MotionDetec
基于System Generator的图像处理工程,多媒体处理FPGA实现的源码,基于视频的运动检测(System Generator based image processing engineering, multimedia processing on FPGA source code, based on video motion detection)
- 2020-10-23 20:57:22下载
- 积分:1
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system
清华大学电子课程设计:Verilog,QuartusII可正确运行,可下载到FPGA上,完成远程通信的整体任务,PC发数据,键盘输入运算符与运算数计算将结果显示在数码管上并返回给PC机,需异步串口调试软件(Verilog, QuartusII run correctly, can be downloaded to the FPGA, to complete the overall task of remote communication, PC send data, keyboard operators and operands calculation displays the results in digital tube and returned to the PC, to be asynchronous serial debugging software)
- 2020-08-16 23:38:25下载
- 积分:1
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RS_Encoder
具有16个校验位的RS编码器,在FPGA上实现。(With 16 RS encoder, the parity bit in the FPGA.)
- 2012-08-06 11:52:37下载
- 积分:1
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MD5
哈希算法FPGA实现代码,采用MD5算法,并给出了仿真波形。(MD5 hashing algorithm for FPGA implementation code)
- 2020-07-03 00:40:02下载
- 积分:1
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VhdlGoldenReferenceGuide
Vhdl Golden Reference Guide.pdf
- 2021-04-23 10:18:48下载
- 积分:1
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b4b52
4b5b编码器实现,初学者资源,简单的逻辑电路实现(4b5b encoder implementation, resources for beginners)
- 2020-12-03 08:59:25下载
- 积分:1