-
03-verilog-11
Verilog reference book
- 2015-02-06 09:03:48下载
- 积分：1
-
This code for countor . it is design in verilog HDL.
This code for countor . it is design in verilog HDL.
- 2022-07-27 18:33:04下载
- 积分：1
-
鸟哥的Linux私房菜——基础学习篇（第四版）
全面了解Linux系统，构建服务器，用Vim写写程序(Fully understand the Linux system, build the server, write programs with Vim.)
- 2018-11-02 10:56:59下载
- 积分：1
-
memristor
忆阻器的SPICE建模模型说明及仿真结果说明(Memristor SPICE modeling and simulation results show that the model describes)
- 2020-11-29 17:09:31下载
- 积分：1
-
eda
EDA 正弦信号发生器：正弦信号发生器的结构有四部分组成，如图1所示。20MHZ经锁相环PLL20输出一路倍频的32MHZ片内时钟,16位计数器或分频器CNT6，6位计数器或地址发生器CN6，正弦波数据存储器data_rom。另外还需D/A0832（图中未画出）将数字信号转化为模拟信号。此设计中利用锁相环PLL20输入频率为20MHZ的时钟，输出一路分频的频率为32MHZ的片内时钟，与直接来自外部的时钟相比，这种片内时钟可以减少时钟延时和时钟变形，以减少片外干扰 还可以改善时钟的建立时间和保持时间，是系统稳定工作的保证。CNT6用来将32MHZ进行8分频得到4096HZ的频率提供给CN6与data_rom时钟信号。由CLK端输入20MHZ的时钟信号，在DOUT端就可输出稳定的正弦信号。(Sine signal generator has the structure of four parts, as shown in figure 1 below. The 20 MHZ phase lock loop PLL20 output all the way of frequency doubled within 32 MHZ slice clock, 16 counter or prescaler CNT6, six counter or address generator CN6, sine data storage data_rom. In addition to D/A0832 (shown in not draw) will digital signal into analog signals. This design using the phase lock loop PLL20 input frequency for 20 MHZ clock, the output of the frequency of all points frequency of 32 pieces (MHZ clock, and comes directly from the external clock, compared to this piece of clock can reduce the clock in delay and clock deformation, to reduce the interference of Can also improve the establishment of the clock time and keep time, is the system stability of assurance. CNT6 used to will and to 8 MHZ get 4096 HZ dividing the frequency to provide CN6 and data_rom clock signal. The input by CLK 20 MHZ clock signal, in DOUT end can output stable sine signals.
)
- 2021-03-07 15:49:29下载
- 积分：1
-
100_Power_Tips_for_FPGA_Designersi
fpga高手设计实战真经100则,最新的FPGA英文书籍，值得参考学习(100 Power Tips for FPGA Designers，The new FPGA English books, worth learning)
- 2013-12-06 19:40:43下载
- 积分：1
-
基于Verilog HDL的16位超前进位加法器
分为3个功能子模块
基于Verilog HDL的16位超前进位加法器
分为3个功能子模块-Verilog HDL-based 16-bit CLA is divided into three functional sub-modules
- 2022-02-05 08:39:21下载
- 积分：1
-
本实施multilplier在vhdl.this源代码是有用的电脑学习…
this implemented multilplier in vhdl.this source code is useful for computer student and hardware engineering.-this is implemented multilplier in vhdl.this source code is useful for computer student and hardware engineering.
- 2022-01-31 00:27:28下载
- 积分：1
-
Digital_filterin_code
MATLAB辅助设计数字滤波器源代码，QUATUS II 实现！(MATLAB-aided design of digital filter source code, QUATUS II implementation!)
- 2009-03-31 13:19:42下载
- 积分：1
-
doing more of a state machine on the three described earlier. Many more informat...
自己做的一个关于more状态机的三种描述的比较。以后会有更多的资料，请大家关注。-doing more of a state machine on the three described earlier. Many more information, please everyone"s attention.
- 2022-02-12 02:20:30下载
- 积分：1
