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audio_verilog
AUDIO音频模块AN831的录音及播放FPGA代码，测试通过(AUDIO audio module AN831 recording and playback of FPGA code, the test passed)
- 2020-09-12 09:27:58下载
- 积分：1
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等精度频率计
基于FPGA的等精度频率计，包括工程，doc和一些查找资料(An equal precision frequency meter based on FPGA, including engineering, Doc, and some lookup data)
- 2020-10-30 21:39:57下载
- 积分：1
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fir在dspbuilder下产生VHDL源码及其测试激励文件时的matlab模型,在modelsim下仿真通过...
fir在dspbuilder下产生VHDL源码及其测试激励文件时的matlab模型,在modelsim下仿真通过-fir in dspbuilder VHDL source code under test and document the incentive mat lab model, the simulation under through modelsim
- 2023-07-19 00:45:03下载
- 积分：1
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基于EPM1270
基于EPM1270的EProm at24c02 驱动-Based on the EPM1270
- 2022-02-27 00:52:37下载
- 积分：1
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DDR SDRAM控制器verilog代码及中文说明文档,对DDR开发很有用的哈。...
DDR SDRAM控制器verilog代码及中文说明文档,对DDR开发很有用的哈。-Verilog source code for DDR SDRAM controler design,including guide book in chinese.
- 2022-03-10 08:09:15下载
- 积分：1
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交通灯电路，南北方向和东西方向分别按绿灯、黄灯、左拐灯、黄灯、红灯的顺序两灭，数码管显示相应的灯亮的时间的倒计时。已通过编译和仿真。...
交通灯电路，南北方向和东西方向分别按绿灯、黄灯、左拐灯、黄灯、红灯的顺序两灭，数码管显示相应的灯亮的时间的倒计时。已通过编译和仿真。-Traffic light circuit, north-south direction and east-west direction respectively green, yellow light, left light, yellow light, red light destroy the order of two, a digital LED display lights the corresponding period of the countdown. Has passed the compilation and simulation.
- 2023-02-22 23:25:03下载
- 积分：1
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wireless_communication_FPGA
数字化，宽带化，是当今无线通信的重点主流方向，FPGA以其功能强大，开发周期短，投资少，可重复修改，开发工具智能及软件可升级等特点成为无线通信首选。(Digital, broadband, is the focus of today s mainstream wireless communications, FPGA with its powerful, short development cycle, low investment, repeatable modify, intelligence and software development tools and other characteristics can be upgraded to become the first choice of wireless communication.)
- 2015-01-30 22:03:45下载
- 积分：1
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CNTRTEST3_7tx_rx_0422
在ISE12.4与TMS320F2812的XINTF接口，实现数据收发(In ISE12.4 TMS320F2812 the XINTF, data transceiver)
- 2021-01-08 10:48:51下载
- 积分：1
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FSM_test for textbanch in vhdl
FSM_test for textbanch in vhdl-FSM_test
- 2022-03-26 05:01:26下载
- 积分：1
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CLZ32
针对32位MIPS微处理器中CLZ指令（对单个字高位连零进行计数）的实现电路，使用了类似于超前进位的逻辑结构。包含测试文档，以及Design
Compile所用的环境和脚本。(The CLZ instruction counts the number of leading zeros in a word. The 32-bit word in the GPR rs is scanned from most-significant to least-significant bit.The number of leading zeros is counted and the result is written to the GPR rd. If
all 32 bits are cleared in the GPR rs, the result written to the GPR rd is 32. )
- 2021-03-31 19:39:08下载
- 积分：1
