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virtex7_pcie_dma
FPGA开发PCIe的源码，采用VHDL语言，通过此源码，能更好的掌握PCIe总线，使开发者少走弯路，
- 2023-01-25 04:55:04下载
- 积分：1
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8BIT_CPU
一个8位的CPU设计，用verilog语言写的，希望有用(A CPU OF 8 BITS
)
- 2020-07-01 09:00:02下载
- 积分：1
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USERMANUL
LPC4357开发板采用ARM的Cortex-M4微控制器LPC4357。内置一个ARM Cortex-M0协处理，CPU运行频率高达204MHz，片内集成1MB Flash和36KB SRAM。开发板采用独立核心板设计，核心板集成64MB SDRAM、128MB NAND-Flash、4MB SPI-Flash。核心板上的摄像头接口可直接连接各种型号的摄像头，两侧160P排针接口引出了除EMC总线外的LPC4357芯片所有功能管脚。
开发板提供丰富的外设接口，包括以太网、液晶屏、摄像头、USB-Host、USB-OTG、SD卡、RS232、RS485、CAN、耳机、麦克风、温度传感器、AD/DA、JTAG仿真器等。此外，开发板提供一个14P扩展接口，包括1路UART、1路SPI、1路I2C、4个IO、3.3V、5V，可以很方便的扩展自己的外围电路。(DS-LPC4357 development board using the Cortex-M4 microcontroller LPC4357 ARM s. A built-in ARM Cortex-M0 co-processor, CPU operating frequency up to 204MHz, 1MB Flash and 136KB SRAM integrated on chip.
Development board using an independent core board design, the core board integrates 64MB SDRAM, 128MB NAND-Flash, 4MB SPI-Flash. Camera core board interface can be directly connected to various types of cameras, both sides 160P pin interface leads to the outside of the bus in addition to EMC LPC4357 chip all the functions of the pins.
Development board provides a rich set of peripheral interfaces, including Ethernet, LCD screen, camera, USB-Host, USB-OTG, SD card, RS232, RS485, CAN, headphone, microphone, temperature sensor, AD/DA, JTAG emulator, etc. . In addition, the development board provides a 14P expansion interfaces, including one-way UART, 1 road SPI, 1 channel I2C, 4 个 IO, 3.3V, 5V, can easily expand their peripheral circuits.)
- 2016-02-23 16:58:53下载
- 积分：1
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8-Multipliers
国外大学上课用PPT。关于乘法器架构，实现，优化，有booth算法的具体实例。(Foreign university classes PPT. About multipliers architecture, implementation, optimization, there is a specific instance of the booth algorithm.)
- 2012-12-06 21:57:36下载
- 积分：1
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ConvolutionWithViterbiDecoding
QPSK调制下的（5,7）卷积码的编码和维特比译码与BPSK调制下（5,7）卷积码的编码和维特比译码的BER特性(QPSK modulation under (5,7) convolutional code encoding and Viterbi decoding and BPSK modulation (5,7) convolutional code encoding and Viterbi BER characteristic)
- 2020-12-12 20:09:15下载
- 积分：1
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er
秒表 东北大学秦皇岛分校 电子设计自动化 实验(Stopwatch Northeastern University at Qinhuangdao electronic design automation experiment)
- 2012-06-27 02:25:14下载
- 积分：1
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zuse
验证阻塞赋值与非阻塞的赋值赋值过程的先后顺序(Verification of the order of assignment and non blocking assignment)
- 2017-12-18 17:04:23下载
- 积分：1
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MifFileGen
VC++6.0软件生成Altera公司FPGA内部存储器ROM初始化数据mif格式文件。方便通过QuartusII导入波形等参数。强调这个是例子，生成的是一个定点的正弦数据表文件，需要用到的请自行修改源代码。(This software generates internal memory ROM initialization mif format data file for FPGA product by Altera. Facilitate the passage of the waveform parameters such as import QuartusII)
- 2013-07-19 02:32:45下载
- 积分：1
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计算机组成原理课程设计(vhdl语言实现)
1. 一位全加器设计
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY add IS
PORT(a,b,cin:IN STD_LOGIC;
Co,S:OUT STD_LOGIC);
END ENTITY add;
ARCHITECTURE fc1 OF add is
BEGIN
S
- 2023-06-03 00:55:02下载
- 积分：1
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此设计采用Verilog HDL硬件语言设计,在掌宇开发板上实现.
将整个电路分为两个子模块，一个提供同步信号（H_SYNC和V_SYNC）及像素位置信息；...
此设计采用Verilog HDL硬件语言设计,在掌宇开发板上实现.
将整个电路分为两个子模块，一个提供同步信号（H_SYNC和V_SYNC）及像素位置信息；另一个接收像素位置信息，并输出颜色信号。这样便于进行图形修改，同时也容易实现- This design uses Verilog the HDL hardware language design,
realizes on the palm space development board Divides into two stature
modules the entire electric circuit, provides the synchronized signal
(H_SYNC and V_SYNC) and the picture element positional information;
Another receive picture element positional information, and output
color signal. Like this is advantageous for carries on the graph to
revise, simultaneously is also easy to realize
- 2022-04-07 13:58:38下载
- 积分：1
