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CORDIC FPGA使用Verilog程序实现
cordic的verilog程序
用ＦＰＧＡ实现-CORDIC FPGA using the Verilog procedures realize
- 2022-05-29 16:40:15下载
- 积分：1
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7-segment
一个7段的显示器，及按一定顺序循环得到的结果，可重复使用(A 7-segment display, and by a certain sequence and cycle the results obtained can be reused)
- 2010-01-10 18:21:33下载
- 积分：1
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行人交通灯系统设计与7段显示
- 2022-08-09 10:50:36下载
- 积分：1
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xilinx_usb_drivers_win10_x64
win10的xilinx usb驱动，较新版本(Xilinx USB driver for win10, newer version)
- 2021-03-11 17:09:26下载
- 积分：1
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picorv32-master
PicoRV32 is a CPU core that implements the RISC-V RV32IMC Instruction Set. It can be configured as RV32E, RV32I, RV32IC, RV32IM, or RV32IMC core, and optionally contains a built-in interrupt controller.
Tools (gcc, binutils, etc..) can be obtained via the RISC-V Website. The examples bundled with PicoRV32 expect various RV32 toolchains to be installed in /opt/riscv32i[m][c]. See the build instructions below for details.
- 2020-06-24 21:40:01下载
- 积分：1
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用VHDL语言仿真音乐设计
用VHDL语言仿真音乐设计
用VHDL语言仿真音乐设计
用VHDL语言仿真音乐设计-Simulation using VHDL language music design music design simulation VHDL language
- 2022-06-30 21:47:10下载
- 积分：1
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这个代码是Verilog HDL。
this Code is in verilog HDL.
This Code is for piplined processor with 4 opcode.
this will work in three cycle latch, decode and exicute..
test bench for xilinx ise is laos given
- 2022-02-12 09:39:12下载
- 积分：1
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AD9250 204b Verilog源码
说明： AD9250是一款双通道14位ADC，最高采样速率250 MSPS，JESD204B Subclass 0或Subclass 1编码串行数字输出(The ad9250 is a dual channel 14 bit ADC with a maximum sampling rate of 250 MSPs and jesd204b sub class 0 or sub class 1 coded serial digital output)
- 2021-04-14 11:01:55下载
- 积分：1
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IIC总线协议，VHDL语言编写，可以直接使用
IIC总线协议，VHDL语言编写，可以直接使用-IIC bus protocol, VHDL language can be used directly
- 2022-07-11 11:04:33下载
- 积分：1
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091655
基于fpga的coms摄像头
扫描，参考文献，(Fpga based on the coms camera scan, reference literature,)
- 2010-08-09 01:03:12下载
- 积分：1
