-
222
说明： VHDL BISS,SSI,ENDAT2.2, ENCODER
- 2020-11-24 17:46:39下载
- 积分：1
-
iic
iic 总线 verilog 源代码
标准i2c总线， 有sda scl 时钟，频率自定(IIC bus standard Verilog source code i2c bus, has sda scl clock, the frequency of self-)
- 2007-10-24 17:52:33下载
- 积分：1
-
cmos-Digital-design
The deep lecture notes for basic digital system for cmos design
- 2012-07-29 17:51:26下载
- 积分：1
-
gmii_tx_mac
实现千兆以太网数据发送，通过GMII接口向PHY写数据，控制PHY发送数据。(Implementation of Gigabit Ethernet data transmission, write data to the PHY through the GMII interface, control PHY data.)
- 2013-08-08 15:24:43下载
- 积分：1
-
Multiplier
A multiplier unit in VHDL
- 2010-01-05 11:42:02下载
- 积分：1
-
层合板刚度
层合板的刚度的计算和验算，包括拉伸刚度A、弯曲刚度D以及耦合刚度B。
首先要给定层合板的各个参数，具体有：层合板的层数N；各单层的弹性常数E1、E2、 、G12；各单层对应的厚度；各单层对应的主方向夹角 。(The stiffness of laminated plates is calculated and checked, including tensile stiffness, A, flexural stiffness, D and coupling stiffness B. First of all, it is necessary to give the parameters of laminated plates, such as the number of plies N, the elastic constants of each layer, E1, E2, and G12, the thickness of each monolayer, and the angle of the main direction corresponding to each single layer.)
- 2021-01-18 09:28:43下载
- 积分：1
-
VHDL-ELEVATOR-CONTORLLER-DESIGN
VHDL电梯控制器程序设计与仿真，内含原理图和VHDL源码，有助于学习VHFL(VHDL u7535 u68AF u63A7 u5236 u5668 u7A0B u5E8F u8BBE u8BA1 u4E0E u4EFF u771F)
- 2017-05-06 15:35:16下载
- 积分：1
-
adder
This the adder VHDL code, it contains input and output fild, also simulate file-adder
- 2022-06-21 18:48:32下载
- 积分：1
-
miaob
电子秒表，FPGA实现,本科某课程设计，程序注释非常详细，(FPGA TIME-COUNTING)
- 2010-05-10 11:25:55下载
- 积分：1
-
High
高速多通道crc实现，可以并行实现5个通道数据的校验，支持10GB以太网标准-High-speed multi-channel crc implementation, can be achieved in parallel 5-channel data validation, support for 10GB Ethernet standard
- 2022-07-18 13:13:37下载
- 积分：1
