-
homework32
说明: 这是32位移位寄存器,是用verilog编写的,能够实现从1到31位的左或右的移位(This is a 32-bit shift register, is prepared verilog, can be realized from the 1-31 shift left or right)
- 2009-07-27 15:54:00下载
- 积分:1
-
对NC Verilog的基本介绍,详细的图解,非常适合初学者使用,一个word文档和一个pdf文档...
对NC Verilog的基本介绍,详细的图解,非常适合初学者使用,一个word文档和一个pdf文档-NC Verilog on the basic introduction, detailed diagrams, very suitable for beginners to use, a word document and a pdf document
- 2022-08-12 19:52:59下载
- 积分:1
-
CJ2
关键词:清华大学计算机系 计算机组成原理大实验 多周期cpu工程源码,内含中断,串口,以及31个指令的实现,读写内存,控制器,ALU,寄存器,分频等模块,小作业什么的可以直接从里面摘抄,为学弟学妹造福(Keywords: Department of Computer Science Computer Composition Principle experimental multi-cycle the cpu Engineering source for the benefit of mentees)
- 2020-12-29 10:09:01下载
- 积分:1
-
axi_jesd204b
ADI JESD204接口的ADC与Xilinx FPGA接口IP,包含Verilog和VHDL源代码,AXI总线接口,ADC串行控制接口(ADI IP for interfacing JESD204 ADC to Xilinx FPGA, include Verilog/VHDL source code, AXI interface and serial config interface
)
- 2021-03-29 15:09:10下载
- 积分:1
-
APF_Series_dq0_ad
串联型有源电力滤波器的 PSCAD仿真,能检测到谐波电压,本仿真的优势是能针对电压跌落或者升高进行自动补偿。(PSCAD simulation of Series type APF (Active Power Filter),this project can dectect the drop of voltage and compensates auomaticly.)
- 2013-03-13 22:51:50下载
- 积分:1
-
GetCPU
动态获取CPU使用率源码 可以加到压力测试里(Dynamic access to CPU use the source code
)
- 2014-06-28 18:56:23下载
- 积分:1
-
Double_Pulse_Test
利用VHDL语言描述出一个双脉冲,可任意设置两脉冲长和中间时间间隔。(A double pulse is described in VHDL language, and the two pulse length and the intermediate time interval can be arbitrarily set.)
- 2020-11-22 12:29:35下载
- 积分:1
-
spi_slave
说明: xilinx 平台的SPI从接口实现源码,供参考学习(used xilinx,slave-spi interface.)
- 2019-04-21 12:08:29下载
- 积分:1
-
经典SOC设计教程
SOC经典教程,包含案例以及完整的代码等等。(SOC classic tutorial, including cases and complete code, and so on.)
- 2020-07-01 22:20:02下载
- 积分:1
-
在spartan-3e上利用八个led实现流水灯效果
在spartan-3e上利用八个led实现流水灯效果-Spartan-3e in the use of eight led lights to achieve the effect of flowing water
- 2022-03-21 18:10:29下载
- 积分:1