登录
首页 » VHDL » CODE_VHDL_AUTO COUNTING 0 TO 9(Đếm từ 0 đến 9 hiển thị 1 led 7 đoạn)

CODE_VHDL_AUTO COUNTING 0 TO 9(Đếm từ 0 đến 9 hiển thị 1 led 7 đoạn)

于 2022-07-22 发布 文件大小:122.93 kB
0 141
下载积分: 2 下载次数: 1

代码说明:

CODE_VHDL_AUTO COUNTING 0 TO 9(Đếm từ 0 đến 9 hiển thị 1 led 7 đoạn)

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • done, would not have introduced the document on the bar, IEEE1364 standard (open...
    做EDA的,就不用介绍这个文件了吧,IEEE1364标准(开放)。-done, would not have introduced the document on the bar, IEEE1364 standard (open).
    2022-03-25 09:59:57下载
    积分:1
  • dotdisplay
    16*16点阵横向移动显示!采用QUARTUS II 9.0编译通过!(16* 16 dot matrix display lateral movement! Compiled by using QUARTUS II 9.0!)
    2011-11-04 22:14:49下载
    积分:1
  • 12_lcd12864
    本实验是用LCD12864显示英文 显示 Our FPGA EDA NIOS II SOPC FPGA(This experiment is shown in English with LCD12864 display Our FPGA EDA NIOS II SOPC FPGA)
    2013-06-26 11:35:54下载
    积分:1
  • rams
    combinatorial modules
    2019-04-13 19:41:21下载
    积分:1
  • 32bit_add_exercise
    32位全加器,另有一个采用流水线的版本,是基于verilog语言的,很实用,希望对大家有所帮助(32-bit full adder, while a pipelined version,code is based on verilog language, it is practical, we hope to help)
    2016-07-19 14:31:17下载
    积分:1
  • taxi
    出租车的计费功能的实现,计量模块、计费模块、控制模块、译码模块。(taxi fee)
    2010-01-16 22:25:33下载
    积分:1
  • AD_R
    AD7685芯片采集程序,可以自行设置采样率,经检验可用。(The AD7685 chip collection procedures, available.)
    2020-12-20 14:19:08下载
    积分:1
  • Multiplier
    圖形介面乘法器,也可自行使用verilog去改(Graphical interface multiplier, also free to use verilog go and change)
    2012-10-25 21:12:49下载
    积分:1
  • 系统设计
    说明:  基于无源蜂鸣器和矩阵按键的电子琴系统设计(design of Electronic Piano System Based on Passive Buzzer and Matrix Key)
    2020-06-21 01:20:08下载
    积分:1
  • utmi
    说明:  介绍USB PHY接口中的UTMI接口, 对使用Verilog进行USB接口编程具有帮助。(This paper introduces UTMI interface in USB PHY interface. It is helpful for programming USB interface with Verilog.)
    2021-03-17 21:39:21下载
    积分:1
  • 696518资源总数
  • 106182会员总数
  • 24今日下载