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这是一篇介绍用verilog语言实现viterbi译码和rake接收机的文章,实用性很强的,在这里也感谢这篇文章的作着...
这是一篇介绍用verilog语言实现viterbi译码和rake接收机的文章,实用性很强的,在这里也感谢这篇文章的作着-This is a description language with verilog viterbi decoding and rake receiver of the article, very practical, here are grateful for this article was
- 2022-05-13 15:53:30下载
- 积分:1
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24x24-booth
可用的24位x24位的booth乘法器的verilog代码(24X24 booth muplily)
- 2011-06-09 17:59:26下载
- 积分:1
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AXI-HP-ZYNQ
用Vivado IPI搭建的Zynq-7000 PS到PL通信过程,使用了AXI-HP接口,利用AXI-DMA IP实现直接读写DDR的过程,软件可以配置传输尺寸。(The Zynq-7000 PS to PL communication process is built by Vivado IPI. AXI-HP interface is used, and AXI-DMA IP is used to read and write DDR directly. The software can configure the transmission size.)
- 2020-12-01 20:39:27下载
- 积分:1
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modsim仿真必备,可以帮助你解决很多你对软件不熟悉的问题!...
modsim仿真必备,可以帮助你解决很多你对软件不熟悉的问题!-Simulation modsim necessary, I can help you solve many of the software you are not familiar with the problem!
- 2022-04-23 10:16:49下载
- 积分:1
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是用VHDL语言写的对A/D转换模块的控制程序,希望对大家有帮助。...
是用VHDL语言写的对A/D转换模块的控制程序,希望对大家有帮助。-VHDL language is used on the A/D conversion module control procedures, in the hope that everyone has to help.
- 2023-05-25 06:40:03下载
- 积分:1
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pn sequence generator
本设计是一个伪随机数发生器。此设计;
- 2023-02-23 15:45:04下载
- 积分:1
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fft
运用matlab实现fft变换,用于地震资料频谱分析!(FFT transform)
- 2013-09-01 16:41:57下载
- 积分:1
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用VHDL实现的DDS逻辑,大家可以参考下
用VHDL实现的DDS逻辑,大家可以参考下-DDS achieved using VHDL logic, we can refer to the following
- 2022-08-10 09:43:58下载
- 积分:1
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VHDLdevelopment-court
vhdl数字电路设计经典教程,入门必备,非扫描版,非常清晰(vhdl digital circuit design classic handbook, entry-essential, non-scan version, very clear)
- 2011-07-13 16:23:18下载
- 积分:1
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fir-filter
11阶fir数字滤波器的verilog程序设计,线性相位,系数量化处理(11 order of fir digital filter verilog programming, linear phase, the coefficient quantization)
- 2012-03-05 10:33:03下载
- 积分:1