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aiqingmaimai
数字钟蜂鸣器音乐——爱情买卖,很时尚的闹钟音乐代码,经测试,很有感觉。(Digital clock buzzer music- love trading, very stylish alarm clock music code, tested, great feeling.)
- 2020-12-28 01:19:01下载
- 积分:1
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基于NIOS的CF卡应用(包括了软件和硬件),ALTERA的IP库中只提供了底层的硬件寄存器描述头文件.这是个基于IP核HAL的软件,以及相应的硬件设计示例....
基于NIOS的CF卡应用(包括了软件和硬件),ALTERA的IP库中只提供了底层的硬件寄存器描述头文件.这是个基于IP核HAL的软件,以及相应的硬件设计示例.-NIOS based on the CF card applications (including the software and hardware), ALTERA the IP library provides only the bottom of the first document describes the hardware registers. This is a HAL-based IP core of the software, hardware design and the corresponding sample.
- 2022-04-25 01:03:08下载
- 积分:1
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基于FPGA芯片,在Nios II IDE软件的开发环境下写的NIos II 软核uart源代码!...
基于FPGA芯片,在Nios II IDE软件的开发环境下写的NIos II 软核uart源代码!-Based on FPGA chip, the Nios II IDE software development environment written in NIos II soft-core uart source code!
- 2022-03-12 11:39:10下载
- 积分:1
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snake
贪吃蛇程序,用verilog实现,可以运行只要修改一下相应的FPGA芯片类型和VGA接口相应的引脚(Snake program, using Verilog to achieve, you can run as long as the appropriate to modify the corresponding FPGA chip type and VGA interface to the corresponding pin)
- 2016-01-16 21:11:14下载
- 积分:1
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bmistree_Project_Proposal
project proposal of verilog language that is gud for beginners
- 2011-04-25 00:31:03下载
- 积分:1
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SRAM 简单测试
SRAM简单测试,测试其性能及其速度,判断SRAM是否可用(Test its performance and speed to determine if SRAM is available)
- 2020-07-10 09:58:55下载
- 积分:1
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8 bit general purpose microprocessor verilog code
它是一种以地址总线数据总线为结构的8位微处理器,主要由两部分组成:一是控制单元,数据通路控制单元控制微处理器的所有块、寄存器和部件,数据通路由地址和数据通路信号处理组成指令读写加法;
- 2022-02-01 07:53:18下载
- 积分:1
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双电梯控制器
说明: 使用verilog实现的双电梯控制器,1-9层,仿真通过(a bi-elevator controller written in VerilgHDL, which has floor1-9, simulation passed)
- 2020-06-17 11:44:27下载
- 积分:1
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VhdlGoldenReferenceGuide
Vhdl Golden Reference Guide.pdf
- 2021-04-23 10:18:48下载
- 积分:1
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GCD
Verilog 最大公约数设计RTL级代码和芯片设计图(Verilog GCD Design and synthesis layout )
- 2021-04-26 15:48:45下载
- 积分:1