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FPGA-timing-constraints
基于Verilog的FPGA设计时序分析约束详细解释与使用方法(FPGA timing constraints)
- 2017-04-24 09:54:35下载
- 积分：1
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DS28E01
用verilog语言实现加密芯片DS28E01的调用操作命令。(Using Verilog language to achieve the encryption chip DS28E01 call operation commands.)
- 2021-03-17 09:49:21下载
- 积分：1
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Roy dsd
说明： basic verilog code on siso, piso, sipo
- 2020-06-25 18:40:01下载
- 积分：1
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viterbi_msk
连续相位调制CPM信号的viterbi编解码(MSK viterbi decode)
- 2012-10-29 23:07:38下载
- 积分：1
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tcdg
Encryption has become a part and parcel of our lives and we have accepted the fact that data is going to encrypted and decrypted at various stages. However, there is not a single encryption algorithm followed everywhere. There are a number of algorithms existing, and I feel there is a need to understand how they work. So this text explains a number of popular encryption algorithms and makes you look at them as mathematical formulas.
- 2014-01-29 15:57:35下载
- 积分：1
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bhas
this is a vhdl program...
- 2013-08-17 23:30:56下载
- 积分：1
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cntl_ddr3(xilinx)
xilinx ddr3最新VHDL代码,通过调试(xilinx ddr3 latest VHDL code through debugging)
- 2007-12-05 23:03:10下载
- 积分：1
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VerilogHDL_DC_Motor_control
采用Verilog HDL语言编写的直流电动机控制系统，主要完成直流电动机的速度控制，典型的三闭环(位置、转速和电流反馈)直流电机控制系统，对控制类相关的学习者价值很高(Using Verilog HDL language of the DC motor control system, mainly the completion of DC motor speed control, a typical three-loop (position, speed and current feedback) DC motor control system for control-type high-value related to the learner)
- 2008-01-10 23:34:29下载
- 积分：1
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cm03pr2
In computer storage, multipath I/O is a fault-tolerance and performance enhancement technique whereby there is more than one physical path between the CPU in a computer system and its mass storage devices through the buses, controllers, switches, and bridge devices connecting them
- 2013-06-09 00:41:09下载
- 积分：1
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This is an FPGA
这个是一个基于FPGA的SDRAM控制器系统，实现对SDRAM的读写操作，用来实现时序的控制-This is an FPGA-based SDRAM controller system, the read and write operations to SDRAM to achieve the control of timing
- 2022-02-02 20:49:24下载
- 积分：1
