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0702
七段数码管显示数字时 使用VHDL语言编写(VHDL The seven-segment LED display digital clock)
- 2013-03-25 22:31:09下载
- 积分：1
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frequence1
基于FPGA的等精度数字频率计，包含FPGA和单片机通信程序，解释非常详细。经过调试成功。(FPGA-based Precision Digital frequency meter, including FPGA and MCU communication program, explained in great detail. After successful commissioning.)
- 2020-10-30 20:29:56下载
- 积分：1
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基于System Generator的最大值求解
最大值求解是利用System Generator平台实现的比较方便不用自己写verilog代码就可以在Xilinx平台下使用，非常方便实用！
- 2023-06-09 16:55:03下载
- 积分：1
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wave_coif3
滤波器的实现，总共为4种，是简单的coif3滤波器的实现方法(The implementation of the filter, a total of 4, is a simple coif3 filter implementation method)
- 2018-03-24 21:05:14下载
- 积分：1
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RC6-block-cipher-using-VHDL
VHDL implementation of RC6 encryption algorithm
Test file represent applying all zero input and all zero key
note that result is correct but bytes positions are swapped
- 2020-12-01 22:09:26下载
- 积分：1
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multiplier.tar
用vhdl实现的booth算法乘法器，包含了multiplexer和rca adder，同时提供了一个测试文件，modelsim测试通过(Algorithm with a booth multiplier vhdl implementation, including a multiplexer and rca adder, while providing a test file, modelsim test pass)
- 2021-04-14 13:18:55下载
- 积分：1
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verilog
一些简单的Verilog代码，小例程，比如求平均值、七段数码管等等(Some simple Verilog code, small routines, such as averaging, seven digital tubes and so on)
- 2016-12-12 10:02:20下载
- 积分：1
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SRAM
SRAM读写测试实例，每秒钟进行一次单字节的SRAM
读和写操作，用chipscope查看时序波形。(SRAM read and write test instances, each time a single byte SRAM
Read and write operations, use chipscope to see the timing waveform.)
- 2017-09-06 11:43:06下载
- 积分：1
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双电梯控制器
说明： 使用verilog实现的双电梯控制器，1-9层，仿真通过(a bi-elevator controller written in VerilgHDL, which has floor1-9, simulation passed)
- 2020-06-17 11:44:27下载
- 积分：1
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SimpleVOut-master
说明： SimpleVOut (SVO) is a simple set of FPGA cores for creating video signals
in various formats. The cores connect using AXI-streams. Most configurations
(resolution, framerate, colordepth, etc.) are set at compile-time using
Verilog parameters. See svo_defines.vh for details on those parameters.
- 2020-06-24 21:20:01下载
- 积分：1
