登录
首页 » Verilog » I2C slave设计代码

I2C slave设计代码

于 2022-03-20 发布 文件大小:1.85 kB
0 162
下载积分: 2 下载次数: 2

代码说明:

I2C slave功能模块的一种实现方式,简单易根据自己实际需求做修改,已经过FPGA验证可以很好的工作

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • xapp1161
    多相滤波系统的设计与实现,有MATLAB仿真程序,有sysgen的系统仿真,还有VHDL代码,其中还有FIR的系数参数等等(Polyphase filter system, the design and implementation includes a MATLAB simulation program, sysgen system simulation, and VHDL code, including FIR coefficient parameters, and so on )
    2021-02-15 17:29:47下载
    积分:1
  • VHDL
    先设计序列发生器产生序列:1011010001101010;再设计序列检测器,检测序列发生器产生序列,若检测到信号与预置待测信号相同,则输出“1”,否则输出“0”,并且将检测到的信号的显示出来。(First design sequence generator sequence: 1011010001101010 redesign sequence detector to detect sequence generator sequence, if the same signal is detected with the preset test signal output " 1" , otherwise " 0" , and the detection display signal out.)
    2015-01-04 12:35:54下载
    积分:1
  • lsd
    按键控制LED流水灯;按键1按下前8个灯从左到右依次点亮,按键2按下中间前8个灯从左到右依次点亮,按键3按下所有灯全亮(Water control button LED lights sequentially lit buttons the eight lights left to right 1 Press button 2 press from left to right is lit in the middle eight lights, key 3 Press All full bright light)
    2012-10-17 18:23:36下载
    积分:1
  • disparity
    Disparity mapp code in VHDL
    2017-11-30 14:48:59下载
    积分:1
  • 61EDA_C1202
    Altera大学计划程序包,基于Nios II的源代码(Altera University program package, based on the Nios II source code)
    2008-08-21 14:46:39下载
    积分:1
  • Poiseuille---BANFANTAN
    格子玻尔兹曼方法模拟poiseuille流,半反弹边界,适合进阶学者(Lattice Boltzmann Simulation poiseuille stream, half rebound border for advanced scholars)
    2021-04-07 13:29:01下载
    积分:1
  • CNN-FPGA-master
    说明:  用FPGA实现CNN算法,实现CNN加速(Realization of CNN Algorithms with FPGA)
    2019-01-21 17:04:03下载
    积分:1
  • uart_fifo
    一份带有FIFO缓存的UART源码,采用verilog编写,实现批量数据的传输,数据缓存量可以通过修改源码中的FIFO的深度来改变。(This is a UART with FIFO. The UART is programmed using verilog, it can transmit or receive batch data. The amount of data buffered can be changed by changing the depth of FIFO.)
    2021-04-25 22:38:46下载
    积分:1
  • verilog HDL语言的综合实验
    BM1拨上实现流水灯功能(用LED灯显示) BM2拨上实现ADC0804功能(用数码管显示) BM3拨上实现TLC5620功能(用数码管显示) BM4拨上实现点阵功能(用16*16点阵显示“欢”) BM5拨上实现LCD1602功能(用1602液晶显示“学号”(第1行),“姓名(拼音)(第2行) BM6拨上实现频率计功能(用数码管显示频率值)
    2022-12-11 15:55:05下载
    积分:1
  • 3input_xor
    用Hspice实现一个三输入异或门,并分析其功耗和延时。(A three input XOR gate is implemented by Hspice, and its power consumption and delay are analyzed.)
    2018-06-12 11:06:45下载
    积分:1
  • 696516资源总数
  • 106481会员总数
  • 12今日下载