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本章介绍了两个EDA技术的综合应用设计实例:数字闹钟和直接数字频率合成器DDS。...
本章介绍了两个EDA技术的综合应用设计实例:数字闹钟和直接数字频率合成器DDS。-EDA chapter describes the two technologies integrated application design example: digital alarm clock and direct digital synthesizer DDS.
- 2023-07-23 01:50:04下载
- 积分：1
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nios_ruanhe_spi_3
这是我自己写的一个摄像头数据存储SD卡程序，quartus的verilog编写，摄像头采用自己添加的外设接口，数据采用dma采集，SD用的是软件自带的SPI内核以及znFAT的文件系统。帧率我没有测，有兴趣的可以测测，初学者可以参考学习，写的代码有点乱，如果有不懂的可以和联系。(This is what I wrote it myself a camera, SD card data storage program, quartus the verilog write, add their own camera with peripheral interfaces, data acquisition using dma, SD with the software that comes with SPI znFAT kernel and file system. I did not measure the frame rate, are interested can Cece, beginners can refer to the study, wrote the code a bit messy, if there do not understand can contact)
- 2015-09-18 11:39:07下载
- 积分：1
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作者：新舜唐日期：2008
--author: Suntion Tang
--date: 2008-6-7
-- two warning
--modify: By Suntion Tang at 2008-6-14
--description: 顶层文件，由于此系统简单，
-- 且底层文件不多，故放弃原理图描述，采用VHDL语言描述-author: Suntion Tang date: 2008-6-7 two warning modify: By Suntion Tang at 2008-6-14 description: the top-level documents, as a result of this system is simple, and not more than the bottom of a document, they give up the schematic description of the use of VHDL language description
- 2022-04-23 09:59:29下载
- 积分：1
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traffic_lights
用Verilog实现的交通信号灯控制，主干道和支路通行的时间不相等(Using Verilog implementation of traffic signal control, the trunk road and the slip is not the same passage of time)
- 2009-03-28 18:31:31下载
- 积分：1
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verilog prescaler for the realization of the odd
verilog实现的奇数分频器 针对任何规模的奇数分频-verilog prescaler for the realization of the odd-numbered odd-numbered points of any size-frequency
- 2022-08-08 15:56:02下载
- 积分：1
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FPGA的存储器代码的VHDL,verilog描述及测试代码
FPGA的存储器代码的VHDL,verilog描述及测试代码-FPGA memory code VHDL, verilog description and test code
- 2022-06-01 08:26:45下载
- 积分：1
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imports
displayport 参考设计，可以对比自己工程做验证，另有参考设计XAPP1178未找到，采用方案为DP159 + Artix7 FPGA(xilinx displayport sink design)
- 2021-01-11 16:58:50下载
- 积分：1
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DDS_DAC_Output
说明： 本工程使用A7系列FPGA产生DDS，用DAC0832进行正弦电压输出(In this project, A7 series FPGA is used to generate DDS, and DAC0832 is used for sinusoidal voltage output)
- 2019-05-06 10:05:10下载
- 积分：1
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本文为verilog的源代码
本文为verilog的源代码-In this paper, the source code for Verilog
- 2022-01-24 19:02:52下载
- 积分：1
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ldpc-for-fpga-decoding
ldpc译码算法的matlab实现，码长960，码率1/2,完全模拟fpga硬件实现语言，量化处理。(ldpc decoding using matalb,code length 960,code rate 1/2)
- 2021-04-12 21:38:56下载
- 积分：1
