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dac7512
实现A/D转换,给定输入，观察输出电压，VHDL程序。(Implement A/D conversion，Given input, observe the output voltage, VHDL program.)
- 2016-04-21 16:05:49下载
- 积分：1
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BPSK
说明： 八相移键控调制的Verilog程序，给出了各个子模块的程序，实现了信号调制。(Eight-phase shift keying modulation of the Verilog program, each module is given the procedures, the signal modulation.)
- 2011-02-24 13:15:15下载
- 积分：1
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CODE_VHDL_INITIALIZING 在 2 线液晶显示，你可以打开/关闭液晶屏 (KHỞI TẠO HIỂN THỊ 2 HÀNG 液晶电视 VÀ CÓ THỂ TẮT/MỞ 液晶屏)
- 2022-05-25 12:11:46下载
- 积分：1
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Over_Current_Relay_Co_ordination
try this for pq improvmnett
- 2012-11-17 05:40:30下载
- 积分：1
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vhdl
vhdl表示与综合，原书第二版，中文版，比较全，用超星打开-vhdl
- 2023-05-18 10:30:04下载
- 积分：1
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spi_master_sent
在FPGA平台实现SPI传输协议开发，SPI为三总线式。(Implementation of SPI transmission protocol development on FPGA platform)
- 2020-08-02 08:18:35下载
- 积分：1
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Combination of shots, quartus2 with the ModelSim FBI put together a detailed ste...
结合截图，quartus2与ModelSim的联调的详细操作步凑，使初学者迅速上手-Combination of shots, quartus2 with the ModelSim FBI put together a detailed step-by-step operation, so that beginners get started quickly
- 2022-03-22 02:04:39下载
- 积分：1
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FSM_Robustness_Testing
基于有限状态机的健壮性测试研究。
关键词：健壮性测试；增强有限状态机；全球平台；安全通道协议(The Research of Robustness Testing Based on FSM)
- 2012-09-06 14:08:56下载
- 积分：1
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VMD642_CPLD
本例程位于 VMD642_CPLD目录中。
使用 CPLD 实现辅助译码、LED 指示灯控制、看门狗等各种逻辑控制电路。源程序使
用 Verilog HDL书写，编译开发系统使用 Cypress公司的 Warp 6.3。(This routine is located VMD642_CPLD directory. Using CPLD implementation auxiliary decoding, LED indicator control, watchdog, and other logic control circuitry. Written using Verilog HDL source code, the compiler development system using Cypress' s Warp 6.3.)
- 2013-09-13 13:59:52下载
- 积分：1
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对于多个子分频的Verilog代码
verilog分频器代码
分为偶数倍分频和奇数倍分频两个verilog源文件 附带一个说明文档-divider verilog code for multiple sub-divided into even and odd frequency divider several times with a two verilog source files documentation
- 2022-10-15 03:40:06下载
- 积分：1
