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matlab_dspbuildings
matlab dsp building 工程欢迎下载(matlab dsp building )
- 2009-12-30 09:17:38下载
- 积分：1
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smartWasher
QUARTER编程环境实现的智能洗衣机系统，通过DE0板子进行模拟，组要完成洗衣机5个步骤的顺序过程以及系统相应动作(QUARTER programming environment of intelligent washing system, through simulation DE0 board, groups 5 to complete the washing process and the system the sequence of steps corresponding action)
- 2020-11-06 13:19:49下载
- 积分：1
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DA(AD768)
AD768产生锯齿波的源码，DA转化的最基本操作。(AD768 sawtooth source code, the basic operation of DA conversion.)
- 2014-03-19 09:39:54下载
- 积分：1
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CameraLink_Oserdes2_test
40M时钟输入经过iserdes倍频到960M(input 40M o clock and output 960M )
- 2014-02-25 14:06:38下载
- 积分：1
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SPWM
基于FPGA的正弦脉宽调制波vhdl代码，同时输出正弦波与SPWM(Sine pulse width modulation wave VHDL code based on FPGA, at the same time with SPWM output sine wave)
- 2021-04-06 23:39:02下载
- 积分：1
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基于FPGA的多路同步脉冲发生器设计1
说明： 采用FPGA（现场可编程门序列）编写VHDL语言设计多路同步脉冲发生器，对信号进行分频处理，实现四路信号相位相差T/16和T/8的延迟相位输出，实现的四路脉冲与传统的脉冲同步器不同，它具有高集成度，高通用性，容易调整和高可靠性等特点。(Using FPGA (field programmable gate sequence) to write VHDL language to design multi-channel synchronous pulse generator, to divide the frequency of the signal, to achieve the four-way signal phase difference T / 16 and T / 8 delay phase output, the realization of the four-way pulse is different from the traditional pulse synchronizer, it has the characteristics of high integration, high-throughput, easy adjustment and high reliability.)
- 2020-03-18 20:52:05下载
- 积分：1
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Synopsys 帮助文件 version 200205
Synopsys 帮助文件 version 200205-Synopsys sold version 200205
- 2023-08-02 16:20:05下载
- 积分：1
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同步串行数据发送电路SSDT的基本功能是将并行数据转换成串行数据并进行同步发送。系统写入和读出时序完全兼容Intel8086时序。
系统以同步信号开始连续发...
同步串行数据发送电路SSDT的基本功能是将并行数据转换成串行数据并进行同步发送。系统写入和读出时序完全兼容Intel8086时序。
系统以同步信号开始连续发送四个字节，在发送中出现5个1时插入一个0，在四个数据发送结束而下一次同步没有开始之前，发送7FH，这时中间不需要插入零
-synchronous serial data transmission circuit SSDT the basic function is to convert parallel data into serial and the same this step. System write and read sequential fully compatible Intel8086 timing. Synchronized signal system to start sending four consecutive bytes, in this emerging 5 1:00 insert a 0, at the end of four data sent and the next synchronization not started before, sending seven FH, then the middle is not inserted
- 2023-05-29 03:45:03下载
- 积分：1
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FPGA
Verilog学习例程EP2C5，内有跑马灯等18个程序(Verilog learning routines EP2C5, marquees and other 18 programs)
- 2020-12-06 22:29:21下载
- 积分：1
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基于fpga和xinlinx ise的usb端口vhdl程序，希望对你有所帮助！
基于fpga和xinlinx ise的usb端口vhdl程序，希望对你有所帮助！-VHDL program for USB port based fpga and xinlinx ise, wish help for you!
- 2022-02-05 00:39:46下载
- 积分：1
