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mimasuo
密码锁 vhdl实现的密码锁 控制程序-mimasuo
- 2022-02-11 23:21:28下载
- 积分：1
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here is realized simple FIFO stack in vhdl.
very simple example, but very help...
here is realized simple FIFO stack in vhdl.
very simple example, but very helpful.
- 2022-03-12 07:44:59下载
- 积分：1
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TOFED_TB_1
A 4 bit twisted ring counter is a sequential circuit which produces the following sequence of
output values: 0000, 1000, 1100, 1110, 1111, 0111, 0011, 0001 and then repeats. Design a
circuit for a 4 bit twisted ring counter that uses four D flip flops. Draw a state transition
diagram, a state table and a schematic for your circuit. Design an alternate implementation
using just three flip flops and draw a state transition diagram, state table and a schematic
for your circuit. If your designs are extended to implement an n bit twisted ring counter,
how many flip flops are required using each of the two approaches. In what situations
would you prefer the first method? In what situations would you prefer the second?
- 2014-11-08 06:58:55下载
- 积分：1
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verilog-digital-system-design-
verilog数字系统设计，一本很好的verilog学习的书籍，很适合初学者(verilog digital system design, a good verilog learning books, it is suitable for beginners)
- 2021-01-10 20:28:50下载
- 积分：1
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High-speed-digital-correlator
16位高速数字相关器的VERIOLOG程序，已经编译通过了，可以使用(16-bit high-speed digital correlator VERIOLOG program has been compiled by, you can use)
- 2020-10-09 11:37:34下载
- 积分：1
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lab2
说明： 使用vivado和Xilinx开发板实现抢答器，开发板为Xilinx Artix-7(Using vivado and Xilinx development board to achieve the responder, the development board is Xilinx artix-7)
- 2021-04-23 01:58:48下载
- 积分：1
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DE2 development company for the altera board SD_Card_Audio examples
用于altera公司DE2开发板上SD_Card_Audio的实例-DE2 development company for the altera board SD_Card_Audio examples
- 2022-12-25 12:55:03下载
- 积分：1
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DDR3_user_design
在Xilinx开发环境ISE13.2上用MIG产生的DDR3 SDRAM控制器，里面生成了Core，可用于DDR3读写控制(On the Xilinx development environment ISE13.2 generated with MIG DDR3 SDRAM controller, which generates the Core, DDR3 can be used to read and write control)
- 2012-02-02 15:16:00下载
- 积分：1
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LCD_test
this a example for the LCD for altera FPGA cyclone ii EP2C8. implemented in verilog. tested using altera EP2C8 fpga
- 2013-07-25 14:43:43下载
- 积分：1
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带同步复位信号的二分频VHDL 程序
带同步复位信号的二分频VHDL 程序-synchronous reset signal with the two-frequency VHDL procedures
- 2022-03-06 12:51:13下载
- 积分：1
