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11_sdi1in_hdmi_out_proc
FPGA SDI 输入，HDMI输出例程(FPGA SDI_IN,HDMI_OUT)
- 2018-07-25 16:30:52下载
- 积分：1
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interr_timer0
interruption routine for PIC16F877
- 2009-12-30 00:43:05下载
- 积分：1
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xilinx 器件vhdl原程序，LCD控制
xilinx 器件vhdl原程序，LCD控制-Xilinx devices VHDL original procedure, LCD control
- 2023-03-04 21:15:04下载
- 积分：1
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一个vhdl实现的hamming码编码器
一个vhdl实现的hamming码编码器-an hamming coder using vhdl
- 2023-02-25 17:20:03下载
- 积分：1
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ADC_Data_Recv_Module
接收机测试输入信号，
生成正余弦波，采样率、频率、幅度、相位可调节
并将生成的数据进行输出
压缩包包括Verilog代码、testbench代码、word文档
matlab仿真代码(The receiver tests the input signal,
Generation of positive cosine wave, sampling rate, frequency, amplitude, phase can be adjusted
And output the generated data
The compressed package includes the Verilog code, the testbench code
Matlab simulation code)
- 2017-12-08 17:56:02下载
- 积分：1
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exercise3
用verilog实现dsp与Fpga接口的同步设计，其功能包括读写操作及四个功能模块，采用两个fifo实现不同时钟域的地址与数据的转换，在quartus ii11.0环境下运行，运行此程序之前需运行将调用fifo。(Dsp using verilog achieve synchronization with Fpga interface design, its features include read and write operations and four functional modules, using two different clock domains to achieve fifo address and data conversion in quartus ii11.0 environment to run, run this program required before running calls fifo.)
- 2013-08-30 11:12:09下载
- 积分：1
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verilog例子资源，对于初学者很有帮助。
verilog例子资源，对于初学者很有帮助。-verilog examples of resources are very useful for beginners.
- 2023-08-15 15:30:03下载
- 积分：1
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DMA
针对QUARTUS的DMA的VHDL代码实现(DMA Controller Code in VHDL)
- 2009-07-04 23:14:32下载
- 积分：1
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logic lock 的vhdl源码，altera平台适用。
logic lock 的vhdl源码，altera平台适用。-logic lock the VHDL source code, altera platform.
- 2023-01-30 09:50:04下载
- 积分：1
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DAC_VHDL
DAC VHDL code using SPI method
- 2016-11-09 19:53:01下载
- 积分：1
