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AD
说明： FPGA控制AD7321的模块，是本人亲自试验过的。有Verilog源码，和简单文档。(FPGA control module of the AD7321 is personally tested. There Verilog source code, and simple document.)
- 2009-08-18 20:31:53下载
- 积分：1
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sin_10k
基于FPGA的利用rom进行查询的方式生成一个频率为10KHZ的sin信号，编译成功，并实现功能仿真。(Query based on the the FPGA use of rom generate a frequency of 10 kHz sin signal, compiled successfully and to achieve functional simulation.)
- 2013-04-23 10:47:17下载
- 积分：1
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等精度测试频率计，包括程序源代码以及相关注释
等精度测试频率计，包括程序源代码以及相关注释-Precision test frequency meter, etc., including source code and related comments ......
- 2022-04-08 21:00:44下载
- 积分：1
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uart
说明： fpga串口收发完整程序，Verilog语言。(FPGA configuration PLL complete program, Verilog language.)
- 2020-06-20 17:00:02下载
- 积分：1
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FPGA 设计的四种常用思想与技巧
FPGA 设计的四种常用思想与技巧-FPGA design ideas and techniques used in four
- 2022-03-15 15:54:37下载
- 积分：1
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VHDL
EDA技术以EDA软件工具为开发环境，以可编程逻辑器件为实验载体，实现源代码编程和仿真功能。VHDL作为一种标准化的硬件描述语言用于描述数字系统的结构、行为、功能和接口。本设计提出了一种基于VHDL语言的编码器和译码器的实现方法。编码器与译码器是计算机电路中基本的器件，本课程设计采用EDA技术设计编码和译码器。编码器由8线-3线优先编码器作为实例代表，译码器则包含3线-8线译码器和2线-4线译码器两个实例模块组成。课程设计采用硬件描述语言VHDL把电路按模块化方式进行设计，然后进行编程、时序仿真和分析等。课程设计结构简单，使用方便，具有一定的应用价值。
(EDA technology take the EDA software as tools for the development of the environment,programmable logic devices in experimental carrier,the realiztion of the source code programming and simulation. The VHDL as a standardized hardware description language used to describe the struction of digital systems,behavior,function and interface. The paper proposes a method for encoder and decoder based on the VHDL language.Encoder and decoder is a basic computer circuit devices.This Curriculum design by EDA design encoder and decoder.Encoders from 8- 3 priority encoder for example,and decoder includes 3- 8 decoder and the 2- 4 examples of the two decoder modules.And then to program, the timing simulation and analysis.Curriculum design, simple structure, easy to use and has a value.)
- 2011-06-22 21:23:30下载
- 积分：1
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verilog时钟分频器~ 50hmz波特率9600bps，使用~
verilog分频器～时钟为50hmz，波特率采用9600bps～-Verilog clock divider ~ 50hmz, using baud rate 9600bps ~
- 2022-06-03 13:21:28下载
- 积分：1
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用VHDL的玛摩尼的ASIC设计
ASIC Design using VHDL by Shyam Mani
- 2022-02-21 17:12:20下载
- 积分：1
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74ls138-integral-4-wire-encoder-16
74ls138组成16..4线编码器 经过本人验证(74ls138 composed of 16 .. 4 line encoder after I verify)
- 2011-09-20 19:00:59下载
- 积分：1
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pipeline_booth_mult_16
用流水线的方法实现16位乘法器，运算速度快，消耗时钟资源少(Pipeline method to realize 16-bit multiplier, which is fast in operation and consumes less clock resources)
- 2020-09-29 18:17:44下载
- 积分：1
