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带load、clr等功能的寄存器
带load、clr等功能的寄存器-belt load, the function clr Register
- 2022-06-20 10:15:42下载
- 积分：1
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16bit-Mulitiplier-Verilog-procedure
这是一个16位乘法器Verilog程序，包括有符号位和无符号位乘法器(This is a 16-bit multiplier Verilog program, including the sign bit and no sign bit multiplier)
- 2012-12-25 11:33:48下载
- 积分：1
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AD9826
AD9826中文说明书 ，对于学习AD9826元件有很大的帮助。(AD9826 Discription in Chinese)
- 2015-04-12 14:22:34下载
- 积分：1
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jesd204_0_ex
说明： jesd204b接收部分程序和带仿真历程(Jesd204b receiving part program and simulation process)
- 2020-11-26 14:49:31下载
- 积分：1
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fir48
48阶FIR设计，采用VHDL语言描述，门级映射……(48-oders FIR design with VHDL language and gate level)
- 2021-04-14 19:38:55下载
- 积分：1
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Project7_5
基于fpga状态机的交通灯设计，亮灯时间自己修改，程序简单易懂。(Traffic light design based on FPGA state machine, light time self-modifying, the program is simple and easy to understand.)
- 2020-06-18 04:00:01下载
- 积分：1
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Giga8b10bv10
说明： altera发布的开源8b10b源代码，vhdl语言描述(altera released the source code open source 8b10b, vhdl language description)
- 2021-01-22 18:18:41下载
- 积分：1
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7 digital display decoder design 7 Digital is pure combinational circuits, usual...
7段数码显示译码器设计7段数码是纯组合电路，通常的小规模专用IC，如74或4000系列的器件只能作十进制BCD码译码，然而数字系统中的数据处理和运算都是二进制的，所以输出表达都是十六进制的，为了满足十六进制数的译码显示，最方便的方法就是利用译码程序在FPGA/CPLD中来实现。例子作为七段译码器，输出信号LED7S的7位分别接数码管的7个段，高位在左，低位在右。例如当LED7S输出为“1101101”时，数码管的7个段g、f、e、d、c、b、a分别接1、1、0、1、1、0、1；接有高电平的段发亮，于是数码管显示“5”。-7 digital display decoder design 7 Digital is pure combinational circuits, usually of small-scale dedicated IC, such as 74 or 4000 Series devices can only be used to decimal BCD decoder, but digital systems in the data processing and computing are binary, so the output expression are hexadecimal, and hexadecimal number in order to meet the needs of the decoding shows that the most convenient way is to use decoding process in FPGA/CPLD in to achieve. Seven-Segment decoder as an example, the output signal of the seven were LED7S access digital pipe 7 above, high in the left, low in the right. For example, when LED7S output as
- 2022-08-11 21:55:01下载
- 积分：1
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一个多路复用器的例子，用VHDL语言写的。
A Mux example written in VHDL.
- 2023-01-13 15:05:04下载
- 积分：1
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myconstellation_final_2
bpsk qpsk 16qam 64qam的constellation(bpsk qpsk 16qam 64qam constellation)
- 2021-03-03 01:49:33下载
- 积分：1
