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用VHDL语言实现的LDPC码的硬件语言实现，对比验证…
用VHDL语言编写的LDPC码硬件实现语言，相对于verilog的，比较简单-Using VHDL language LDPC code hardware implementation language, compared to Verilog, and relatively simple
- 2023-05-19 11:55:03下载
- 积分：1
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n_bit_paralleLoadShiftRegJK
n_bit_paralleLoadShiftRegJK
- 2017-11-17 17:27:49下载
- 积分：1
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complex_timing_by_Primetime
用PrimeTime的技巧，解决复杂时钟问题。(The world of telecommunications chips is full of messy clocking situations. This paper will cover the tricks and tehniques that author Paul Zimmer has developed to avoid the need to pour over reams of timing reports looking for problems. Best paper winner at SNUG San Jose 2001!)
- 2012-08-05 19:07:47下载
- 积分：1
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seg7
SEG7数码管显示示例程序，适用于ALTERA的CPLD(SEG7 digital display sample program of ALTERA CPLD)
- 2012-05-31 10:29:25下载
- 积分：1
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EGO1快速上手指南v1224
EGO1快速上手指南，适用于新手进行学习(EGO1 Quick Start Guide)
- 2020-12-08 20:29:20下载
- 积分：1
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8-fft
FFT 8 PT RDX 2 USING VERILOG
- 2014-03-31 02:35:31下载
- 积分：1
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这是一个HDB3编码器，可以将普通的二进制序列转化为符合HDB3编码规则的双极性序列...
这是一个HDB3编码器，可以将普通的二进制序列转化为符合HDB3编码规则的双极性序列-This is a HDB3 encoder, can be transformed into an ordinary binary sequences in order to comply with the rules of HDB3 bipolar coding sequence
- 2022-12-15 13:45:03下载
- 积分：1
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使用VHDL实现锁相环,是个学习VHDL的好例子,与众分享
使用VHDL实现锁相环,是个学习VHDL的好例子,与众分享-PLL using VHDL, VHDL is learning a good example, sharing with the public
- 2023-08-12 00:15:02下载
- 积分：1
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nco11000
实现输入一正弦波和噪声的叠加，介绍详细欢迎下载(The input of a superposition of sine wave and noise introduced in detail)
- 2010-05-16 14:19:53下载
- 积分：1
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dianti
6层电梯设计，采用vhdl编写，能够实验电梯功能(6-story elevator design, using vhdl prepared, able to lift function experiments)
- 2014-04-06 11:41:34下载
- 积分：1
