-
CODE_VHDL_INITIALIZING 在 2 线液晶显示,你可以打开/关闭液晶屏 (KHỞI TẠO HIỂN THỊ 2 HÀNG 液晶电视 VÀ CÓ THỂ TẮT/MỞ 液晶屏)
- 2022-05-25 12:11:46下载
- 积分:1
-
fpga
简易数字存储示波器verilog源代码 经过EP2C8Q208C8验证(Simple digital storage oscilloscope verilog source code has been verified EP2C8Q208C8)
- 2013-07-16 13:04:03下载
- 积分:1
-
the_last
VHDL语言实现两个人掷骰子游戏,最多6次,大者胜则结束游戏并在点阵上显示,一直平手则一直进行直到达到6次。(Achieving the dice game between two people by using VHDL language.The maximum number of times is 6.The game will over when there is a biger one in one time,otherwise,the game will continue until the time of the game is up to 6.)
- 2021-01-21 12:18:42下载
- 积分:1
-
17_walsh_128
walsh码,在CDMA系统中经常使用到的方法,在quartusII环境下实现的。(walsh code in the CDMA system, the method often used in quartusII environment to achieve.)
- 2020-07-03 09:00:02下载
- 积分:1
-
perl
说明: perl学习资料,包含一些常用的一些文档,可直接做来用于实践(perl training)
- 2009-08-21 10:48:17下载
- 积分:1
-
modelsim_ug
Mentor Graphics ModelSim User s Guide Software v6.3g
- 2010-04-18 13:30:25下载
- 积分:1
-
clock_smg
自己做的数码管显示的时钟 一个非常简单的FPGA时钟 用累加做的(To do their own digital display clock of the FPGA clock is a very simple to do with the cumulative)
- 2011-09-27 21:07:54下载
- 积分:1
-
DDR(双速率)SDRAM控制器参考设计,xilinx提供
DDR(双速率)SDRAM控制器参考设计,xilinx提供-DDR (double data rate) SDRAM controller reference design for Xilinx
- 2022-11-19 10:30:03下载
- 积分:1
-
my_or
verilog 或门程序 初学者必备。。。。。。。。。。。。(verilog )
- 2009-05-26 16:07:42下载
- 积分:1
-
matlab123
多个MATLAB设计滤波器的方法程序以及图形实现(number MATLAB filter design methods and procedures and Graphics)
- 2006-12-27 23:07:56下载
- 积分:1