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shizhong
VHDL写时钟，分频模块什么，实现计时。定点报时，定点闹钟，显示年月日。(verilog HDL)
- 2014-01-09 18:29:40下载
- 积分：1
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FPGA realize for a good vga display routines, vhdl language.
针对FPGA一个实现vga显示的很好的例程，vhdl语言编写。-FPGA realize for a good vga display routines, vhdl language.
- 2022-01-24 09:45:51下载
- 积分：1
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hssdrc IP核的可配置的通用SDRAM控制器的自适应银行…
HSSDRC IP core is the configurable universal SDRAM controller with adaptive bank control and adaptive command pipeline.
HSSDRC IP core and IP core testbench has been written on SystemVerilog and has been tested in Modelsim.
HSSDRC IP core is licensed under MIT License
- 2022-09-20 22:10:03下载
- 积分：1
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FPGA
基于FPGA的FFT处理器的实现，适合做fpga的工程技术人员参考-FPGA-based realization of the FFT processor, suitable for the engineering and technical personnel fpga reference
- 2022-09-26 01:05:03下载
- 积分：1
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UART模块用VHDL。
用VHDL语言编写的串口通讯模块，可以实现发送和接受功能。-A UART module writen in VHDL.
- 2022-12-24 06:35:03下载
- 积分：1
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这是spi接口传输的一部分内容，本源码一共三部分，功能：spi接口的的实现即对外设的读写数据...
这是spi接口传输的一部分内容，本源码一共三部分，功能：spi接口的的实现即对外设的读写数据-This is the spi interface transfer part of the contents of a total of three parts of this source, function: spi interface that the realization of the read and write data to the peripheral
- 2022-01-30 17:08:30下载
- 积分：1
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SD_verilog
说明： 该代码，只用了硬件描述语言Verilog在完成对SD卡控制器的编写，经济实用(The code, only the hardware description language Verilog in the completion of the SD card controller to prepare, economical and practical)
- 2020-12-27 22:19:02下载
- 积分：1
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A very useful IP core resources, which includes the JTAG, MEMORY, PCI, SDRAM, an...
非常有用的IP核资源，里面包含了JTAG,MEMORY,PCI，SDRAM和USB1.1等内容，期望对大家有用-A very useful IP core resources, which includes the JTAG, MEMORY, PCI, SDRAM, and USB1.1 and other content, expectations for all of us
- 2022-03-03 12:55:22下载
- 积分：1
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altera EP1C6Q240C6开发板原理图
altera EP1C6Q240C6开发板原理图-altera EP1C6Q240C6 SCH
- 2022-12-08 05:45:03下载
- 积分：1
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vhdl实现8255,可重用，ALATEK公司提供验证，用说明文档
vhdl实现8255,可重用，ALATEK公司提供验证，用说明文档-achieve VHDL 8255, reusable, ALATEK companies to provide certification, with documentation
- 2023-06-28 21:30:03下载
- 积分：1
