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sd模型
完整的Verilog验证模型，包括设备完整的状态。(Complete verilog Verification Model)
- 2020-06-16 09:00:01下载
- 积分：1
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FIR
说明： 一个1MHz的FIR低通滤波器。
① 时钟信号频率16MHz;
② 输入信号位宽8bits，符号速率16MHz；
③ 要求在Matlab软件中进行FIR滤波器浮点和定点仿真，并确定FIR滤波器抽头系数；
④ 写出测试仿真程序。(A 1MHz FIR low pass filter.
(1) The clock signal frequency is 16MHz;
(2) The input signal has a bit width of 8 bits and a symbol rate of 16 MHz;
(3) Floating-point and fixed-point simulation of FIR filter is required in Matlab software, and tap coefficients of FIR filter are determined.
(4) Write the test simulation program.)
- 2019-06-19 21:47:13下载
- 积分：1
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ulpiereport.tar
开源的ULPI IP核，可用于USB3300芯片的开发(openSource ULPI IP core which could be used for USB3300 chip development)
- 2020-07-02 06:40:02下载
- 积分：1
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Риторика_Зачетная работа
access must be conf urr arr
- 2019-05-29 20:23:53下载
- 积分：1
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multi16
有符号16位乘法器。经典booth编码。拓扑结构为wallance树。加法器类型是进位选择加法器。(Number system: 2 s complement
Multiplicand length: 16
Multiplier length: 16
Partial product generation: PPG with Radix-4 modified Booth recoding
Partial product accumulation: Wallace tree
Final stage addition: Carry select adder
)
- 2013-01-01 14:13:58下载
- 积分：1
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altera
altera官方的各种有用的参考资料，都是自己收集的，遇到问题可以很方便的查看(altera official variety of useful references, are their own collection, problems can easily view)
- 2014-06-02 10:39:18下载
- 积分：1
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CNN-FPGA-master
说明： 用FPGA实现CNN算法，实现CNN加速(Realization of CNN Algorithms with FPGA)
- 2019-01-21 17:04:03下载
- 积分：1
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8253
8253可编程定时器/计数器芯片 VeriLog实现(8253 programmable timer/counter chip VeriLog achieve)
- 2013-05-31 20:40:23下载
- 积分：1
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8b10b Verilog
采用verilog语言基于查找表描述8b10b编码源代码(Using Verilog language to describe 8B10B encoding source code based on look-up table)
- 2021-01-27 14:58:41下载
- 积分：1
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SD卡控制器verilog
sd卡读写，仿真模型，testbanch测试文件(sdcard read write and sdcard model)
- 2021-04-21 16:28:49下载
- 积分：1
