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                        DigitalClock
                        
                          数字钟:实验中用到的小程序,用于万年历中的模块(Digital clock: a small program used in the experiment, the modules for calendar)                         
                            - 2013-05-26 09:25:23下载
- 积分:1
 
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                        wrpc-v2.0_src.tar
                        
                          About 1588 PTP protocol xillinx FPGA running code and Software application, and to introduce documents, want to help everyone                         
                            - 2021-04-14 16:38:55下载
- 积分:1
 
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                        LAB22
                        
                          应用verilog编程语言控制VGA显示屏显示一幅图片。(Application verilog programming language control VGA display shows a picture.)                         
                            - 2016-10-27 16:30:12下载
- 积分:1
 
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                        DE2_PS2_Example
                        
                          PS2 Module for Altera DE2                         
                            - 2017-06-20 21:04:32下载
- 积分:1
 
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                        vga
                        
                          vga,显示彩条,及其简单易懂,适合初学(vga, display color bars, and its easy-to-understand, suitable for beginners)                         
                            - 2012-10-10 21:10:15下载
- 积分:1
 
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                        FLASH_PCB
                        
                          M25P64-SPI-FLASH芯片的FPGA控制程序,已仿真验证(M25P64- SPI- FLASH chip FPGA control program, simulation)                         
                            - 2020-08-28 16:48:12下载
- 积分:1
 
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                        DCT_IDCT
                        
                          H264/AVS中的离散余弦变换DCT以及反离散余弦变换IDCT的Verilog代码(H264/AVS the discrete cosine transform and inverse discrete cosine transform DCT IDCT of Verilog code)                         
                            - 2011-06-11 07:08:30下载
- 积分:1
 
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                        ASK编码(Verilog通过,内含Testbentch)
                        
                          `timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
//creat for the zedboard . 
//The AD used ADV7511.
//////////////////////////////////////////////////////////////////////////////////
module ad(
datain , clk , rst , dataout );
    input [11:0] datain;
    input clk;
    input rst;   
    output [11:0] dataout;                         
                            - 2022-01-25 20:47:44下载
- 积分:1
 
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                        src
                        
                          yuv444 与yuv422相互转换verilog语言(yuv444 to yuv422)                         
                            - 2021-01-20 14:38:41下载
- 积分:1
 
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                        FPGA ‘for’ 循环
                        
                          Verilog 语言编写的for循环,用来验证在FPGA中是否能想在C中那样编写for循环,结果证明虽然仿真可以得到正确的结果,但是在真正的工程中进行编译时耗时24小时都没完成,所以选择其他的方法进行循环操作,毕竟FPGA是并行的,而C中是串行的思想。                         
                            - 2022-06-19 04:55:07下载
- 积分:1