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分数时延FIR
说明： 分数时延FIR滤波器FPGA设计的相关资料及软件无线电实验平台MFSS6842使用说明(Fractional delay FIR filter FPGA design related information and software radio experimental platform MFSS6842 instructions)
- 2019-11-18 22:45:35下载
- 积分：1
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10_rom_test
介绍如何使用 FPGA 内部的 ROM 以及程序对该 ROM 的数据读操作。(This paper introduces how to use the ROM inside the FPGA and how to read the data of the ROM by the program.)
- 2019-03-30 16:39:57下载
- 积分：1
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VGAtuxiangxianshi
用FPGA实现 VGA显示的图像显示控制器设计
用VHDL实现 硬件实现是屏幕上面出现彩色条纹(VGA display with FPGA image display controller design
Using VHDL hardware implementation is colored stripes appear above the screen)
- 2014-05-19 14:07:57下载
- 积分：1
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usbd_ucos
基于ALINX AX7020硬件平台的USB-OTG通信程序。操作系统采用uCOS III v1.41，基本实现了双向USB2.0 块传输（Bulk Transfer）通信，zynq的PS端接收USB数据并回传至主机。经测试，主机端Window10系统采用libUSBK编程时，采用64字节的块时，传输速率可达210Mbps。zynq开发工具为Vivado2015.4，程序包中包含了全部的硬件和软件工程文档。(A USB-OTG communication project where an AX7020 platform is employed as USB device. The embeded operating system is uCOS III of version 1.41, and the FPGA toolchain is Vivado 2015.4. This project implements a full speed bidirectional USB2.0 bulk transfer. A test on Windows 10 host with libUSBK shows that the transfer speed is up to 201Mbps.)
- 2020-09-09 09:38:02下载
- 积分：1
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DIATAL_MATLAB_FPGA_AlteraVerilog
[数字通信同步技术的MATLAB与FPGA实现——AlteraVerilog版]书中资源代码，非常好，分享，
希望大家下下！( U651 u0B3 u09108 u09108 u0103 u0101 u7801 uFF0C u975E u5HR U597D uFF0C u5206 u4EAB uFF0C u5E0C u671B u5927 u5BB6 u4E0B u4E0B uFF01)
- 2017-05-11 13:47:58下载
- 积分：1
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Verilog_Basic
说明： Verilog 入门,如果你要很了解Verilog你不用先谖完一本厚厚的书还弄不清楚Verilog到底在干啥事,这份资料有助於快速了斛Verilog(Verilog Basic, If you try very hard to understand verilog by read a thick book, try read this first you will get a quick understanding of verlog.)
- 2010-03-19 09:02:22下载
- 积分：1
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adc_dac
ADC-DAC transmittion works thru SPI on 25 MHZ. Used for some student project on Xilinx sprtan3a FPGA
- 2016-12-01 19:44:33下载
- 积分：1
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Advanced-FPGA-Design
高级FPGA设计__结构、实现和优化,中文翻译版(Advanced FPGA Design- Architecture, Implementation, and Optimization)
- 2021-04-01 11:09:08下载
- 积分：1
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VHDL语言实现时钟程序，用fpga开发板试过后，能够执行
VHDL语言实现时钟程序，用fpga开发板试过后，能够执行-VHDL Pang Sung-wife of mother
- 2022-05-27 01:05:27下载
- 积分：1
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veval
It is vhdl code for defining a finite state machine
- 2009-08-07 18:06:13下载
- 积分：1
