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openmips
一个开源mips处理器verilog 源码(wishbone interface wishbone interface)
- 2020-08-16 15:48:32下载
- 积分:1
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signaltap_user_guide
signaltap 中文说明,内容详细。
ALTERA signaltap USER GUIDE IN CHINESE(ALTERA signaltap USER GUIDE IN CHINESE)
- 2011-12-03 23:50:21下载
- 积分:1
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mc8051 a good learning materials in absolute authority of the official website
mc8051 很好的学习资料 官网的绝对权威-mc8051 a good learning materials in absolute authority of the official website
- 2022-09-20 10:05:03下载
- 积分:1
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pl_read_write_ps_ddr
说明: PL 和 PS 的高效交互是 zynq 7000 soc 开发的重中之重,常常需要将 PL 端的大量数据实时送到 PS 端处理,或者将 PS 端处理结果实时送到 PL 端处理,但是各种协议非常麻烦,灵活性也比较差,直接通过 AXI 总线来读写 PS 端 ddr 的数据,这里面涉及到 AXI4 协议,vivado 的 FPGA 调试等。(The efficient interaction between PL and PS is the top priority of zynq 7000 SoC development. We often need to send a large amount of data from PL to PS for real-time processing, or send the processing results from PS to pl for real-time processing. In general, we will think of using DMA for processing, but various protocols are very troublesome and the flexibility is poor. This course explains how to use Axi directly Bus to read and write DDR data of PS terminal, which involves axi4 protocol, FPGA debugging of vivado, etc.)
- 2021-01-22 17:46:44下载
- 积分:1
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FPGA——IP_RAM实验
说明: FPGA——IP_RAM实验:
创建IPRAM核,单端口,10位地址线(256字节),8位数据线(每字节8byte),读写使能
input [9:0] address;
input clock;
input [7:0] data;
input wren; //置1则写入
output [7:0] q;
LNXmode:控制LEDC显示
1:mode1,从k1~k3输入data的低4位,ledb计时,从0~f,计时跳变沿读取k1~k3的值,存入RAM
8个数之后,从RAM输出数据,用leda显示,同样每秒变化一次(The experiment of FPGA-IP_RAM:
Create IPRAM core, single port, 10 bit address line (256 bytes), 8 bit data line (8 byte per byte), read and write enablement)
- 2020-06-22 04:20:02下载
- 积分:1
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基于SOPC EP2C5开发板的I2C总线的A/D D/A例程
基于SOPC EP2C5开发板的I2C总线的A/D D/A例程-A/D AND D/A routings interfaced with i2c based on sopc ep2c5
- 2022-01-25 22:27:04下载
- 积分:1
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adc0809用FPGA控制的采样非常好用的实例 自己看书后终结的
adc0809用FPGA控制的采样非常好用的实例 自己看书后终结的-ADC0809
- 2022-09-16 00:25:02下载
- 积分:1
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本文件解压后clock_time.vhd采用编程环境maxplusII,完成时间秒定时、记时,设置时间秒、声光报警等功能。...
本文件解压后clock_time.vhd采用编程环境maxplusII,完成时间秒定时、记时,设置时间秒、声光报警等功能。-this document unpacked clock_time.vhd maxplusII use programming environment, the time for completion seconds timing, Hutchison, the set-up time seconds, sound, light, alarm functions.
- 2022-07-03 03:02:23下载
- 积分:1
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GTX4
光纤发送接收模块,verilog编写,主要用于光纤的发送和接收,波长1310nm(Fiber optic transmitter receiver module, verilog written primarily for transmitting and receiving the optical fiber, wavelength 1310nm)
- 2016-06-28 14:06:40下载
- 积分:1
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8B_10BENCODER
基于8B10B的编解码模块的设计,使用verilog HDL语言,具有实用价值。(8B10B encoder)
- 2014-05-23 16:39:25下载
- 积分:1