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time_echo
GPS接收机相关器中关于积分清零模块、历元计数模块、时钟模块、以及整个相关器(accumulator、epoch counter、time base、gps baseband)
- 2015-08-28 23:47:56下载
- 积分:1
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sobel-with-verilog-language
用verilog实现sobel边缘检测算法(sobel edge detection with verilog language)
- 2020-07-12 19:38:53下载
- 积分:1
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src
yuv444 与yuv422相互转换verilog语言(yuv444 to yuv422)
- 2021-01-20 14:38:41下载
- 积分:1
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ahb_interface
AHB BUS, Master Slave Arbiter -- example(AHB BUS, Master Slave Arbiter)
- 2020-11-23 10:39:35下载
- 积分:1
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DW8051单片机的设计,用HDL设计,详细的HDL设计
DW8051单片机的设计,用HDL设计,详细的HDL设计-DW8051 microcontroller design, HDL design, detailed design of the HDL
- 2023-03-12 10:35:03下载
- 积分:1
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ZEDBOARD
ZEDBOARD的管脚分配图和约束文件,包括PCB图和xdc文件(Pin assignment of ZEDBOARD)
- 2021-03-23 21:19:15下载
- 积分:1
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vending-machine
用Verilog实现自动售货机功能,代码较初级。易懂,内含test文件。(Automatic vending machines function with Verilog code than the primary. Understandable, containing test files.)
- 2013-11-30 20:25:34下载
- 积分:1
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VHDL的循环冗余校验发生器和接收器
VHDL cyclic redundancy check generator und receiver
- 2022-01-23 11:24:26下载
- 积分:1
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uart
说明: 串口通信通用模块,FPGA Verilog语言 ise,vivado环境(uart,FPGA Verilog, ise,vivado)
- 2020-06-22 07:20:01下载
- 积分:1
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2D4N_com
2维4节点的UEL单元,嵌入UMAT,采用j2 mises屈服准则(2d4nodes uel elements, with umat codes, and j2 mises flow rule)
- 2014-06-04 20:43:21下载
- 积分:1