-
ug948-design-files
Xilinx Sysgen User Guide
- 2018-10-14 21:54:22下载
- 积分:1
-
cordic_atan
说明: 用verilog语言实现计算反正切函数,在软件无线电中解调PM/FM中使用的尤为频繁。上传的压缩包是modelsim工程,基于6.5c,里边包含一个完整的PM波产生以及解调过程的matlab文件仿真,并取其中间的I和Q支路做为verilog文件的输入,并将其借条输出与MATLAB实际解调输出作比较。
鉴相器的设计基于CORDIC算法,其精度取决于迭代的深度。由于工程实际运用只需要解调出atan值,并不需要绝对的值,所以并没有给予加权,需要的同学可以自己加上。(Calculated using verilog language arc tangent function, the software radio demodulation PM/FM is particularly used frequently. From the archive is modelsim project, based on 6.5c, inside the PM contains a complete demodulation process of wave generation and simulation matlab file, and whichever is the middle of the I and Q branch verilog file as input, and its IOU demodulated output and actual output of MATLAB for comparison. Phase detector design is based on CORDIC algorithm, its accuracy depends on the iteration depth. As the practical application of engineering demodulated atan value only and does not need absolute value, and there is no weight given to the need of the students can add their own.)
- 2010-04-07 16:30:47下载
- 积分:1
-
fft
FPGA实现FFT算法的源代码及工程文件,此工程为ISE工程项目。有详细的说明,可以运行。(FPGA Implementation of FFT algorithm source code and project files, this works for the ISE project. There are detailed instructions, you can run.)
- 2013-10-12 17:21:32下载
- 积分:1
-
12_lcd12864
本实验是用LCD12864显示英文
显示
Our FPGA EDA
NIOS II
SOPC
FPGA(This experiment is shown in English with LCD12864 display Our FPGA EDA NIOS II SOPC FPGA)
- 2013-06-26 11:35:54下载
- 积分:1
-
simple_cpu
初学cpu结构的很好的verilog代码的示例,适合初学者(novice cpu structure of the good verilog code examples for beginners)
- 2007-03-03 01:05:16下载
- 积分:1
-
cordic
说明: 16级流水线型cordic旋转代码以及测试文件,亲测好用(16-stage pipelined cordic rotation code and test files, pro-testing)
- 2019-03-09 08:59:01下载
- 积分:1
-
xapp1251
说明: 1. REVISION HISTORY
2. OVERVIEW
3. SOFTWARE TOOLS AND SYSTEM REQUIREMENTS
4. DESIGN FILE HIERARCHY
5. INSTALLATION AND OPERATING INSTRUCTIONS
6. SUPPORT
- 2020-11-07 09:49:49下载
- 积分:1
-
SDRAM读写控制的实现与Modelsim仿真
1. 本实例用于控制开发板上面的SDRAM完成读写功能;先向SDRAM里面写数据,然后再将数据读出来做比较,如果不匹配就通过LED变亮显示出来,如果一致,LED就不亮。2. part1目录是使用Modelsim仿真的工程;3. part2目录是在开发版上面验证的工程;
- 2022-01-30 11:24:06下载
- 积分:1
-
walsh
沃尔什函数发生器工程文件,Quartus Ⅱ 13.0版本(Walsh Function Generator)
- 2020-07-03 08:20:01下载
- 积分:1
-
help_lib
1.JESD204B协议
2.Xilinx的JESD204B phy 核手册
3.Xilinx的JESD204B rx_tx 核手册7.1
4.Xilinx的JESD204B rx_tx 核手册7.2
5.verilog实现串口发送(1.JESD204B protocol
2.Xilinx JESD204B PHY core manual
3.Xilinx JESD204B rx_tx core manual 7.1
4.Xilinx JESD204B rx_tx core manual 7.2
5.verilog to achieve serial transmission)
- 2017-11-15 16:09:22下载
- 积分:1